M65665SP Datasheet, PDF (1/15 Pages) Mitsubishi Electric Semiconductor – PICTURE-IN-PICTURE SIGNAL PROCESSING

MITSUBISHI DIGITAL TV ICs
M65665SP/FP
PICTURE-IN-PICTURE SIGNAL PROCESSING
DESCRIPTION
APPLICATION
The M65665SP/FP is a PIP (Picture in Picture) signal
NTSC, PAL-M, PAL-N color TV
processing LSI, whose sub-picture input is composite
signal or component signals(Y /C or Y /U/V) f or NTSC, RECOMMENDED OPERATING CONDITIONS
PAL-M, and PAL-N. The built-in f ield memory (168k-bit
RAM) , V-chip data slicer and analog circuitries lead the
high quality PIP sy stem low cost and small size.
FEATURES
Supply v oltage range ------------------------ 3.2 ~ 3.5 V
Operating f requency ----------------------- 14.32 MHz
Operating temperature ------------------------ 0 ~ 70 deg.
Input v oltage (CMOS interf ace) "H" ----- VDD x 0.7 ~ VDD V
"L" ----- 0 ~ VDD x 0.3 V
Output current ( output buf f er ) ------------ 4 mA ( MAX )
Output load capacitance ---------------------- 20 pF ( MAX ) *1
Circuit current ----------------------------------- - mA
* Internal V-chip data slicer (f or sub-picture)
* Vertical f ilter f or sub-picture ( Y signal )
* Base band comb f ilter (2 Line)
NOTICE: Connect a 0.1µF or larger capacitor between VDD and VSS pins.
*1 : Include pin capacitance ( 7 pF )
* Single sub-picture ( selectable picture size : 1/9 , 1/16 )
* Sub-picture processing specif ication ( 1/9 , 1/16 size) :
Quantization bits Y , B-Y, R-Y : 7 bits
Horizontal sampling 229 pixels (Y ), 57 pixels (B-Y , R-Y )
Vertical lines
69/ 52 lines
* Frame ( sub-picture ) on/of f
* Built-in analog circuits :
Two 8-bit A/D conv erter (f or sub-picture signal)
Three 8-bit D/A conv erters (f or Y , U and V of sub-picture)
Sy nc-tip-clamp, VCXO,OSD switch ... etc..
* IIC BUS control ( parallel/serial control) :
PIP on/of f , Frame on/of f ( programmable luma lev el),
Block diagram & Application examples
Shown next pages
Sub-picture size ( 1/9, 1/16 ),
PIP position ( f ree position ), Picture f reeze ,
Y delay adjustment, Chroma lev el, Tint, Black lev el,
Contrast
...etc..
PIN CONFIGURATION (TOP VIEW)
SWM 1
OSD_SEL 2
SDATA 3
SCLK ⁴
DVdd ⁵
DVss ⁶
BGPS ⁷
SCK ⁸
BGPM 9
FSC ¹⁰
T E S T 5 ¹¹
TESTEN ¹²
SWMG ¹³
RESET ¹⁴
CSYNCS 15
AVdd(ad) 16
Vin(ad) 17
Uin(ad) 18
Vrb 19
Yin(ad) 20
Vrt ²¹
42 _Y(R)OUT
41 _{OSD_RIN}
40 _AGndDA
39 _U(G)OUT
38 _{OSD_GIN}
37 _VZ
36 V(B)OUT
35 _{OSD_BIN}
34 _VddDA
33 _VD
32 _HD
31 _AVss(vcxo)
30 X'tal(P-N)
29 _X'tal(P-M)
28 X'tal(NT )
27 BIAS
26 _Filter
25 _AVdd(vcxo)
24 _CVBSin(ad)
23 AVss(ad)
22 _Cin(ad)
Outline 42 Pin SDIP Package (M65665SP)
Outline 0.8mm pitch 42 Pin SOP Package (M65665FP)
MITSUBISHI
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