M65617SP Datasheet, PDF (1/15 Pages) Mitsubishi Electric Semiconductor – PICTURE-IN-PICTURE SIGNAL PROCESSING

MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
DESCRIPTION
This system is an NTSC system PinP system that accommodates
subscreen composite input and main screen Y/C input. It is a
semiconductor IC circuit having a built-in 96K bit field memory and
an analog circuit, which permits a low-cost and compact system
configuration.
FEATURES
• Built-in field memory 96K bit for PIP
• Built-in luminance signal vertical filter
• No. of subscreen displays: 1 (two sizes, 1/9 and 1/16, can be
selected from.)
• No. of subscreen samples (1/9 - 1/16 sizes)
No. of quantization bits: 6 for all Y, B-Y and R-Y
No. of horizontal picture elements: 171(Y), 28.5 (B-Y, R-Y)
No. of vertical lines: 69/52
• Subscreen frame display ON/OFF
• Built-in analog circuits such as sync chip clamp, VCXO, and ana-
log switch
• Built-in 2 channels of 8 bit A/D converter
(for main signal burst lock and PIP sub signal)
• Built-in two channels of 8 bit D/A converter (luminance and
chroma signals)
• I²C bus control
Controls: display ON/OFF, display size selection, setting of
display position, frame ON/OFF, setting of frame level, selection
of frame animation/field still image, setting of Y delay amount,
color level, tint, black level, etc.
APPLICATION
TV
RECOMMENDED OPERATING CONDITION
Supply voltage range........................................................3.1 to 3.5V
Operating frequency.........................................................14.32 MHz
Operating temperature....................................................-10 to 75°C
Input voltage (CMOS interface) "H"........................VDD×0.7 to VDD V
"L".............................0 to VDD×0.3V
Output current (output buffer)........................................±4mA (MAX)
Output load capacitance............................................20pF (MAX) ^∗1
Circuit current.........................................................................140mA
NOTICE: Connect a 0.1µF or larger capacitor between VDD and VSS
pins.
∗1 : Include pin capacitance (7pF)
PIN CONFIGURATION (TOP VIEW)
AVss3 (vcxo) 1
VCXO out 2
VCXO in 3
FILTER 4
BIAS 5
AVdd3 (vcxo) 6
AVdd2 (m) 7
Vin (m) 8
Vrt (m) 9
Vrb (m) 10
AVss2 (m) 11
AVdd1 (s) 12
Vin (s) 13
Vrt (s) 14
Vrb (s) 15
AVss1 (s) 16
RESET 17
DVss1 18
DVdd1 19
BGP(s)/TEST0 20
SCK 21
CSYNC(s)/TEST1 22
ACK 23
DATA 24
CLK 25
DVss2 26
52 AVssf (ana)
51 Cin
50 TESTEN
49 Yin
48 TEST9
47 Y-PIP
46 TEST8
45 C-PIP
44 AVdd4 (da)
43 C-PIPin
42 AVss4 (da)
41 Y-PIPin
40 ADJ-Ysub
39 Yout-sub
38 ADJ-Csub
37 Cout-sub
36 DVss3 (ram)
35 DVdd3 (ram)
34 SWMG/TEST7
33 VD/CSYNC/TEST6
32 HD/TEST5
31 SWM/TEST4
30 MCK
29 fsc/TEST3
28 BGP(m)/TEST2
27 DVdd2
Outline 52P4B
1