M62230FP Datasheet, PDF (1/4 Pages) Mitsubishi Electric Semiconductor – LCD MATRIX REGULATOR

MITSUBISHI (Dig./Ana. INTERFACE)
M62230FP
LCD MATRIX REGULATOR
DESCRIPTION
The M62230FP is a semiconductor circuit for LCD matrix regulator,
which will generate the diveded-voltage to drive LCD matrix.
By changing the connection of R pin(i.e.,Change the internal
resistor ratio), M62230FP can support divided voltage ratio ranging
from 1/5 bias to 1/13 bias.
The high stability and any desired voltage levels is possible, since
the variable voltage regulator for Vref is built-in.
FEATURES
•Adjustable type voltage divider.
(The setting range of internal resistor is from 1/5 bias to 1/13
bias)
•5 resident buffer-Amp. (5 divided output)
•Low power dissipation(1.8 mA Typ.)
•Resident voltage-variable regulator for Vref.
PIN CONFIGURATION (TOP VIEW)
R6 1
R5 2
R4 3
R3 4
R2 5
R1 6
REGOUT 7
REGIN 8
VIN3 9
VIN2 10
20 VREF
19 VIN5
18 VCC
17 VO5
16 VO4
15 VO3
14 VO2
13 VO1
12 GND
11 VIN
Outline 20P2N-A
APPLICATION
To drive LCD.
RECOMMEND OPERATING CONDITIONS (Ta=25°C)
Supply voltage range : GND-Vcc :(if V 1 > -1V, it is necessary to
support V IN)........ -30 to -10V
Recommend input voltage GND-VREF :VREF ≥ Vcc........ -30 to -6V
(To set Vcc, VREF, in order that both I 0-V2 I & I VCC-V5 I
are larger than 1V)
BLOCK DIAGRAM
REGIN 8
VIN3 9
VIN2 ¹⁰
GND 12
VIN 11
REGOUT
7
-1.38V
R1
R2
R3
R4
6
5
4
3
R
R
4R
R
R
R
R
R
R
R
R
13
14
15
16
17
VO1
VO2
VO3
VO4
VO5
2 R5
1 _R6
20 _VREF
19 _VIN5
18 _VCC
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