M5M54R16AJ-10 Datasheet, PDF (1/7 Pages) Mitsubishi Electric Semiconductor – 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM

1998.11.30 Ver.B
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI LSIs
M5M54R16AJ,ATP-10,-12,-15
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M54R16A is a family of 262144-word by 16-bit
static RAMs, fabricated with the high performance CMOS
process and designed for high speed application. These
devices operate on a single 3.3V supply, and are directly
TTL compatible.
They include a power down feature as well. In write
and read cycles, the lower and upper bytes are able
to be controled either togethe or separately by LB
and UB.
FEATURES
•Fast access time
M5M54R16AJ,ATP-10 ... 10ns(max)
M5M54R16AJ,ATP-12 ... 12ns(max)
M5M54R16AJ,ATP-15 ... 15ns(max)
•Single +3.3V power supply
•Fully static operation : No clocks, No refresh
•Common data I/O
•Easy memory expansion by S
•Three-state outputs : OR-tie capability
•OE prevents data contention in the I/O bus
•Directly TTL compatible : All inputs and outputs
•Separate control of lower and upper bytes by LB and UB
PIN CONFIGURATION (TOP VIEW)
A0
1
A1
2
ADDRESS
INPUTS
A2
3
A3
4
A4
5
CHIP SELECT
INPUT
S
6
DQ1
7
DATA
DQ2 8
INPUTS/
OUTPUTS DQ3
9
DQ4 10
(3.3V) VCC 11
(0V) GND 12
DQ5 13
DATA
INPUTS/
DQ6
14
OUTPUTS ^DQ7 15
WRITE
DQ8 16
CONTROL INPUT W 17
ADDRESS
INPUTS
A5 18
A6 19
A7 20
A8 21
A9 22
44 A17
ADDRESS
43 A16
INPUTS
42
A15
OUTPUT
41 OE ENABLE INPUT
40 UB
BYTE
39 LB
CONTROL
INPUTS
38 DQ16
37 DQ15 DATA
36
DQ14
INPUTS/
OUTPUTS
35 DQ13
34 GND (0V)
33 VCC _(3.3V)
32 DQ12
31 DQ11 DATA
30
DQ10 ^INPUTS/
OUTPUTS
29 DQ9
28 N.C
27 A14
26
A13 _ADDRESS
25 A12
INPUTS
24 A11
23 A10
Outline 44P0K
APPLICATION
High-speed memory system
PACKAGE
M5M54R16AJ .......... 44pin 400mil SOJ
M5M54R16ATP .......... 44pin 400mil TSOP(II)
FUNCTION
The operation mode of the M5M54R16A is determined
by a combination of the device control inputs S, W, OE,
LB, and UB. Each mode is summarized in the function
table.
A write cycle is executed whenever the low level W
overlaps with low level LB and/or low level UB and low
level S. The address must be set-up before write cycle
and must be stable during the entire cycle.
The data is latched into a cell on the traling edge of
W, LB, UB or S, whichever occurs first, requiring the
set-up and hold time relative to these edge to be
maintained. The output enable input OE directly
controls the output stage. Setting the OE at a high level,
the output stage is in a high impedance state, and the
data bus contention problem in the write cycle is
eliminated.
A read cycle is excuted by setting W at a high level
and OE at a low level while LB and/or UB and S are in
an active
state. (LB and/or UB=L, S=L)
When setting LB at a high level and other pins are in
an active state, upper-Byte are in a selectable mode
in which both reading and writing are enable, and
lower-Byte are in a non-selectable mode. And when
setting UB at a high level and other pins are in an
active state, lower-Byte are in a selectable mode in
which both reading and writing are enable, and upper-
Byte are in a non-selectable mode.
When setting LB and UB at a high level or S at high
level, the chip is in a non-selectable mode in which
both reading and writing are disabled. In this mode,
the output stage is in a high-impedance state,
allowing OR-tie with other chips and memory
expansion by LB, UB and S.
Signal-S controls the power-down feature. When S
goes high, power dissapation is reduced extremely.
The access time from S is equivalent to the address
access time.
MITSUBISHI
ELECTRIC
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