M54975P Datasheet, PDF (1/5 Pages) Mitsubishi Electric Semiconductor – Bi-CMOS 8-BIT SERIAL-INPUT LATCHED DRIVER

MITSUBISHI <CONTROL / DRIVER IC>
M54975P/FP
Bi-CMOS 8-BIT SERIAL-INPUT LATCHED DRIVER
DESCRIPTION
The M54975 is a semiconductor integrated circuit fabricated using
Bi-CMOS technology. It contains a serial input to serial/parallel
output 8-bit CMOS shift register and CMOS latch as well as bipolar
8-bit parallel-output driver.
FEATURES
q Serial input to serial/parallel output
q Cascade connections possible through serial output
q Latch circuit included for each stage
q Enable input for output control
q Low supply current .................................. ICC ≥ 10µA at standby
q Serial input/output level is compatible with standard CMOS
q Driver : Withstand voltage ...................................... BVCEO ≥ 30V
Large drive current ................................ (IO(max)=300mA)
q Wide operating temperature range ..................... Ta=-20 – +75°C
APPLICATION
Thermal printer head dot driver, Serial-to parallel conversion, Relay
and Solenoid driver
FUNCTION
The M54975 consists of an 8-bit D-type flip-flop, the output of
which is connected to 8 latches.
When data is applied to the serial data input (S-IN) and a clock
pulse is applied to clock input (T), an “L” to “H” change of the clock
will cause the data input signals to enter the internal shift registers
and the data in the shift registers will be shifted in order.
PIN CONFIGURATION (TOP VIEW)
Clock
Serial input
T→ 1
S-IN → 2
Logic GND L-GND 3
VCC 4
Serial output S-OUT ← 5
Latch input LATCH → 6
Enable input
EN 7
Driver GND P-GND 8
16 → O1
15 → O2
14 → O3
13 → O4
12 → O5
11 → O6
10 → O7
9 → O8
Outline 16P4(P)
16P2N-A(FP)
Parallel outputs
Using a number of M54975 units for bit expansion in series will
entail connecting serial output (S-OUT) to S-IN of the next-stage
M54975.
In parallel output, when the latch input is set to “H” and the output-
control input (enable input EN) is “L”, a clock pulse changing from
“L” to “H” will cause the serial data input signal to appear at output
O1, and the data will be shifted in order at outputs O2 – O8.
The parallel output will yield a signal that is inverted with respect to
the serial data input.
Setting the LATCH input to “L” will prevent data from entering the
latch.
When the EN input is set to “H”, all outputs (O1 – O8) will be set to
OFF. Since the internal logic state of the IC is uncertain at power-
on time, set the EN input to “H” (and outputs O1 – O8 will set to
BLOCK DIAGRAM
Parallel outputs
O1
O2
O3
O4
O5
O6
O7
O8
16
15
14
13
12
11
10
9
Power supply
VCC 4
8 P-GND Driver GND
Enable input
EN 7
Latch input LATCH 6
Serial input S-IN 2
Clock
T1
Q
Q
Q
Q
Q
Q
Q
Q
LD LD LD LD LD LD LD LD
DQ DQ DQ DQ DQ DQ DQ DQ
T
T
T
T
T
T
T
T
3
L-GND
Logic GND
5 S-OUT Serial output