SP5730 Datasheet, PDF (6/14 Pages) Mitel Networks Corporation – 1.3GHz Low Phase Noise Frequency Synthesiser

SP5730
Preliminary Information
When the device receives a valid address byte, it pulls
the SDA line low during the acknowledge period, and
during following acknowledge periods after further data
bytes are received. When the device is programmed into
read mode, the controller accepting the data must pull the
SDA line low during all status byte acknowledge periods
to read another status byte. If the controller fails to pull the
SDA line low during this period, the device generates an
internal STOP condition, which inhibits further reading.
Write mode
With reference to Table 2, bytes 2 and 3 contain
frequency information bits 2¹⁴-2⁰ inclusive. Byte 4 and
byte 5 control the reference divider ratio, see Table 1,
charge pump setting, see Table 6, REF/COMP output,
seeTable 7, output ports and test modes, see Table 4.
After reception and acknowledgement of a correct ad-
dress (byte 1), the first bit of the following byte determines
whether the byte is interpreted as a byte 2 or 4, a logic ‘0’
indicating byte 2, and a logic ‘1’ indicating byte 4. Having
interpreted this byte as either byte 2 or 4 the following
data byte will be interpreted as byte 3 or 5 respectively.
Having received two complete data bytes, additional
data bytes can be entered, where byte interpretation
follows the same procedure, without readdressing the
device. This procedure continues until a STOP condition
is received. The STOP condition can be generated after
any data byte, if however it occurs during a byte transmis-
sion, the previous byte data is retained. To facilitate
smooth fine tuning, the frequency data bytes are only
accepted by the device after all 15 bits of frequency data
have been received, or after the generation of a STOP
condition.
Read mode
When the device is in read mode, the status byte read
from the device takes the form shown in Table 2.
Bit 1 (POR) is the power-on reset indicator, and this is set
to a logic ‘1’ if the Vcc supply to the device has dropped
below 3V (at 25°C), e.g. when the device is initially turned
ON. The POR is reset to ‘0’ when the read sequence is
terminated by a STOP command. When POR is set high
this indicates that the programmed information may
have been corrupted and the device reset to power up
condition.
Bit 2 (FL) indicates whether the device is phase locked,
a logic ‘1’ is present if the device is locked, and a logic ‘0’
if the device is unlocked.
Programmable features
RF programmable
divider
Function as described above
Reference programmable
divider
Function as described above.
Charge pump current
The charge pump current can be pro
grammed by bits C1-C0 within data byte
5, as defined in Table 6.
Test mode
The test modes are invoked by bits REB.
RS, T1 and T0 as described in Table 4.
Reference/Comparison
frequency output
The reference frequency Fref or
comparison frequency Fcomp can be
switched to the REF/COMP output,
function as defined in Table 7.
RE and RS default to logic ‘I’ during
device power up, thus enabling the
comparison frequency Fcomp at the
REF/COMP output.
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