GP2015 Datasheet, PDF (6/24 Pages) Mitel Networks Corporation – GPS Receiver RF Front End

GP2015
PIN DESCRIPTIONS
All V_EE and V_CC/V_DD pins must be connected to ensure correct operation
Pin No.
1
2
3
4,6
5
7
8
9
10
11
12, 13
14
15
16
17
Signal Name
IFOutput
Input/Output
Output
PLL Filter 1
Output
PLL Filter 2
Output
V_EE (OSC)
V_CC (OSC)
V_EE (REG)
PRef
Input
Input
Input
Input
PReset
Output
V_EE (IO)
CLK
Input
Input
N/C
MAG
Output
SIGN
Output
OPClk-
Output
OPClk+
Output
Description
IF Test output.
Connected to output of Stage 3 prior to the A to D converter.
A series 1kΩ resistor is incorporated for buffering purposes.
PLL Filter 1.
Connected to the bias network within the on-chip VCO. An
external PLL loop filter network should be connected between
this pin and PLL Filt 2 (see below).
PLL Filter 2.
Connected to the varactor diodes within the on-chip VCO. An
external PLL loop filter network should be connected between
this pin and PLL Filt 1 (see above).
Negative supply to the on-chip VCO. (See Note 1)
Positive supply to the on-chip VCO.
Negative supply to the VCO regulator.
This must be connected to GND.
Power-on Reset Reference input.
An on-chip comparator produces a logic HI when the PRef
input voltage exceeds +1.21V. (Nom) (See Page 3)
Power-on Reset Output.
A TTL compatible output controlled by the Power-on reset
comparator (See above). This output remains active even
when the chip is powered down. (See pin 19 - PDn).
Negative supply to the Digital Interface. (See Note 2)
Sample Clock input from the correlator chip.
A TTL compatible input (which operates at 5.714MHz if used
with GP2021 correlator device) used to clock the MAG & SIGN
output latches, on the rising edge of the CLK signal.
Not connected. (See Note 4)
Magnitude bit data output.
A TTL compatible signal, representing the magnitude of the
mixed down IF signal. Derived from the on-chip 2-bit A to D
converter, synchronised to the CLK input clock signal.
Sign bit data output.
A TTL compatible signal, representing the polarity of the mixed
down IF signal. Derived from the on-chip 2-bit A to D converter,
synchronised to the CLK input clock signal.
40MHz Clock output - inverse phase.
One side of a balanced differential output clock, with opposite
polarity to Pin 17 - OPClk+. Used to drive a master-clock signal
within the correlator chip.
40MHz Clock output - true phase.
Other side of a balanced differential output clock set, with
opposite polarity to Pin 16 - OPClk-. Used to drive a master-
clock signal within the correlator chip.
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