MT9162 Datasheet, PDF (5/17 Pages) Mitel Networks Corporation – ISO2-CMOS 5 Volt Single Rail Codec

Advance Information
MT9162
For synchronous operation, data is sampled from
Din, on the falling edge of BCL during the time slot
defined by the STB input. Data is made available, on
Dout, on the rising edge of BCL during the time slot
defined by the STB input. Dout is tri-stated at all
times when STB is not true. If STB is valid, then quiet
code will be transmitted on Dout during the valid
strobe period. There is no frame delay through the
PCM serial circuit for synchronous operation.
Applications
Figure 4 shows the MT9162 in a line card
application.
For asynchronous operation Dout and Din are as
defined for synchronous operation except that the
allowed output jitter on Dout is larger. This is due to
the resynchronization circuitry activity and will not
affect operation since the bit cell period at 128 kb/s
and 256 kb/s is relatively large. There is a one frame
delay through the PCM serial circuit for
asynchronous operation. Refer to the specifications
of Figures 5 & 6 for both synchronous and
asynchronous SSI timing.
PWRST
While the MT9162 is held in PWRST no device
control or functionality is possible.
0.1 µF
VBias
1 µF
( ) Typical External Gain
AV= 5-10
Input from Subscriber
Line Interface
0.1 µF
1
20
+5V
100k
2
19
3
18
100k
1k
100k
1k
A/µ
RxMUTE
TxMUTE
4
17
5 ^MT9162 ₁₆
6
15
+5V
7
14
100k
8
13
1k
9
12
100k ^CS0
10
11
1k
100k ^CS1
Out to Subscriber Line
Interface
1k
100k CS2
1k
DC to DC
+5V
Converter
Din
From Digital
Phone
Twisted Pair
Lin
MT8972 _Dout
Z_T
DNIC
Frame Pulse
Lout
Clock
Figure 4 - Line Card Application
7-165