MT8816 Datasheet, PDF (5/6 Pages) Mitel Networks Corporation – ISO-CMOS 8 x 16 Analog Switch Array

ISO-CMOS MT8816
AC Electrical Characteristics^† - Crosspoint Performance-Voltages are with respect to V_DD=5V, V_SS=0V,
V_EE=-7V, unless otherwise stated.
Characteristics
Sym Min Typ^‡ Max Units
Test Conditions
1 Switch I/O Capacitance
2 Feedthrough Capacitance
3 Frequency Response
Channel “ON”
20LOG(V_OUT/V_Xi)=-3dB
4 Total Harmonic Distortion
(See G.5, G.6 in Appendix)
5 Feedthrough
Channel “OFF”
Feed.=20LOG (V_OUT/V_Xi)
(See G.8 in Appendix)
C_S
C_F
F_3dB
THD
FDT
20
0.2
45
0.01
-95
pF
pF
MHz
%
dB
f=1 MHz
f=1 MHz
Switch is “ON”; V_INA = 2Vpp
sinewave; R_L = 1kΩ
See Appendix, Fig. A.3
Switch is “ON”; V_INA = 2Vpp
sinewave f= 1kHz; R_L=1kΩ
All Switches “OFF”; V_INA=
2Vpp sinewave f= 1kHz;
R_L= 1kΩ.
See Appendix, Fig. A.4
6 Crosstalk between any two
X_talk
-45
channels for switches Xi-Yi and
Xj-Yj.
-90
Xtalk=20LOG (V_Yj/V_Xi).
-85
(See G.7 in Appendix).
-80
dB V_INA=2Vpp sinewave
f= 10MHz; R_L = 75Ω.
dB V_INA=2Vpp sinewave
f= 10kHz; R_L = 600Ω.
dB V_INA=2Vpp sinewave
f= 10kHz; R_L = 1kΩ.
dB V_INA=2Vpp sinewave
f= 1kHz; R_L = 10kΩ.
Refer to Appendix, Fig. A.5
for test circuit.
7 Propagation delay through
t_PS
switch
30
ns R_L=1kΩ; C_L=50pF
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5dB better.
AC Electrical Characteristics^† - Control and I/O Timings- Voltages are with respect to V_DD=5V, V_SS=0V,
V_EE=-7V, unless otherwise stated.
Characteristics
Sym Min Typ^‡ Max Units
Test Conditions
1 Control Input crosstalk to switch CX_talk
30
(for CS, DATA, STROBE,
Address)
mVpp V_IN=3V squarewave;
R_IN=1kΩ, R_L=10kΩ.
See Appendix, Fig. A.6
2 Digital Input Capacitance
C_DI
10
pF f=1MHz
3 Switching Frequency
F_O
20 MHz
4 Setup Time DATA to STROBE
t_DS
10
ns R_L= 1kΩ,
5 Hold Time DATA to STROBE
t_DH
10
ns R_L= 1kΩ,
6 Setup Time Address to STROBE t_AS
10
ns R_L= 1kΩ,
7 Hold Time Address to STROBE
t_AH
10
ns R_L= 1kΩ,
8 Setup Time CS to STROBE
t_CSS
10
ns R_L= 1kΩ,
9 Hold Time CS to STROBE
t_CSH
10
ns R_L= 1kΩ,
10 STROBE Pulse Width
t_SPW 20
ns R_L= 1kΩ,
11 RESET Pulse Width
t_RPW 40
ns R_L= 1kΩ,
12 STROBE to Switch Status Delay t_S
40 100
ns R_L= 1kΩ,
13 DATA to Switch Status Delay
t_D
50 100
ns R_L= 1kΩ,
14 RESET to Switch Status Delay
t_R
35 100
ns R_L= 1kΩ,
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
Digital Input rise time (tr) and fall time (tf) = 5ns.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
ΠRefer to Appendix, Fig. A.7 for test circuit.
C_L=50pF ^Œ
C_L=50pF ^Œ
C_L=50pF ^Œ
C_L=50pF ^Œ
C_L=50pF ^Œ
C_L=50pF ^Œ
C_L=50pF ^Œ
C_L=50pF ^Œ
C_L=50pF ^Œ
C_L=50pF ^Œ
C_L=50pF ^Œ
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