SP5054 Datasheet, PDF (4/9 Pages) Mitel Networks Corporation – 2.6GHz 3-Wire BUS Controlled Synthesiser

SP5054
Fig. 3 Block diagram of SP5054
Mode
3
2
1
0
Mode Select input voltage
0·925V_CC to V_CC
0·675V_CC to 0·825V_CC
Open circuit
Programmable
divider bit
length
14
15
15
Reference
divider
ratio
512
512
1024
Frequency
step size
(kHz) *
125
125
62·5
Maximum
operating
frequency (GHz) *
2·0479
2·5
2·0479
0V to 0·325 V_CC
15
640
100
2·5
Table 1 SP5054 modes of operation. * Frequencies stated apply when using a 4MHz crystal.
FUNCTIONAL DESCRIPTION
The SP5054 contains all the elements necessary, with the
exception of reference crystal, loop filter and external high
voltage transistor, to control a voltage controlled local oscilla-
tor, so forming a PLL frequency synthesised source.
The system is controlled by a microprocessor via a stand-
ard Data, Clock and Enable three-wire data bus.
The data load normally consists of a single word, which
contains the frequency and port information, and is only
transferred to the internal data shift register during an enable
high period.
The clock input is disabled during enable low periods. New
data words are only accepted by the internal data buffers from
the shift register on a negative transition of the Enable, so
giving improved fine tune facility for digital AFC etc.
The data sequence and timing follows the format shown in
Fig. 4.
The frequency is set by loading the programmable divider
with the required 14/15 bit divisor word. The output of this
divider, F_PD, is fed to the phase comparator where it is
compared in phase and frequency domain to the internally
generated comparison frequency, F_COMP.
F_COMP is obtained by dividing the output of an on-chip
crystal controlled oscillator. The crystal frequency used is
generally 4MHz, which gives an F_COMP of 3·90625/6·25/
4
7·8125kHz and, when multiplied back up to the synthesised
LO, gives a minimum step size of 62·5/100/125kHz, respec-
tively.
The programmable divider is preceded by an input RF
preamplifier and high speed, low radiation prescaler. The
preamplifier is arranged to be self oscillating, so giving excel-
lent input sensitivity.
The SP5054 contains an improved lock detect circuit
which generates a flag when the loop has attained lock. ‘In
lock’ is indicated by high impedance state.
The SP5054 contains 4 general purpose open collector
outputs, ports P1-P4, which are capable of sinking at least
10mA. These outputs are set by the remaining four bits within
the normal data word.
NOTES ON PIN COMPATIBILITY
The SP5054 may be used in SP5055 applications which
require 3-wire bus as opposed to I²C bus data format. In
SP5055 applications where the reference crystal is grounded
to pin 3, a small modification is required to ground the crystal
as shown in Fig. 5.
Appropriate connections must also be made to the Mode
Select input (see Table 1). In Mode 3, The SP5054 is pro-
gramming compatible with the Toshiba TD6380, in Modes 0
and 2 with the TD6381 and in Mode 1 with the TD6382.