MT9196 Datasheet, PDF (36/38 Pages) Mitel Networks Corporation – ISO2-CMOS Integrated Digital Phone Circuit (IDPC)

MT9196
Preliminary Information
AC Electrical Characteristics^† - SSI BUS Asynchronous Timing (note 1) (see Figure 14)
Characteristics
Sym
Min
Typ^‡
Max Units Test Conditions
1 Bit Cell Period
2 Frame Jitter
3 Bit 1 Dout Delay from STB
going high
4 Bit 2 Dout Delay from STB
going high
5 Bit n Dout Delay from STB
going high
T_DATA
T_j
t_dda1
t_dda2
t_ddan
600+
T_DATA-T_j
600 +
(n-1) x
T_DATA-T_j
7812
3906
600
T_j+600
600+
T_DATA
600 +
(n-1) x
T_DATA
600 +
T_DATA+T_j
600 +
(n-1) x
T_DATA+T_j
ns BCL=128 kHz
ns BCL=256 kHz
ns
ns C_L=150 pF, R_L=1K
ns C_L=150 pF, R_L=1K
ns C_L=150 pF, R_L=1K
n=3 to 8
6 Bit 1 Data Boundary
T_DATA1 T_DATA-T_j
T_DATA+T_j
ns
7 Din Bit n Data Setup time from t_SU
T_DATA\2
STB rising
+500ns-T_j
+(n-1) x
ns n=1-8
T_DATA
8 Din Data Hold time from STB
t_ho
T_DATA\2
ns
rising
+500ns+T_j
+(n-1) x
T_DATA
† Timing is over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
NOTE 1: Not production tested, guaranteed by design.
T_j
STB
Dout
Din
70%
30%
70%
30%
t_dda1
70%
30%
t_dda2
t_dha1
Bit 1
T_DATA1
t_ho
t_su
Bit 2
Bit 3
T_DATA
D1
T_DATA/2
T_DATA
D2
D3
T_DATA
NOTE: Levels refer to % V_DD (CMOS I/O)
Figure 14 - SSI Asynchronous Timing Diagram
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