MT8930C-1 Datasheet, PDF (35/42 Pages) Mitel Networks Corporation – CMOS ST-BUS™ FAMILY Subscriber Network Interface Circuit

MT8930C
AC Electrical Characteristics^† - Intel Bus Interface Timing (Ref. Figure 24 & 25)
Characteristics
Sym Min Typ^‡ Max Units
Test Conditions
1 Chip select setup time
t_CSS
10
ns
2 Chip select hold time
t_CSH
25
ns
3 Address Latch pulse width
t_ALW
50
ns
4 Address setup time
t_ADS
20
ns
5 Address hold time
t_ADH
20
ns
6 Data setup time - Write
t_DWS
35
ns
7 Data hold time - Write
t_DHW
20
ns
8 Data output delay - Read
t_DOD
240 ns 50 pF load
9 Data hold time - Read
t_DHR
25
90
ns 50 pF load
10 Write pulse width
t_WPW
60
ns
11 RD, WR delay
t_RWD
60
ns
12 Read pulse width
t_RPW 240
ns
13 Read setup time
t_RDS
20
ns
† Timing is over recommended temperature & power supply voltages
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
CS
ALE
AD0-7
WR
RD
V_IH
V_IL
t_CSS
V_IH
V_IL
t_ALW
t_CSH
t_ADS
t_ADH
t_RWD
t_DHW
V_IH
V_IL
V_IH
V_IL
t_RDS
V_IH
V_IL
Address
Data in
t_WPW ^tDWS
Figure 24 - Intel Bus Interface Timing (Write Cycle)
CS
ALE
AD0-7
RD
WR
V_IH
V_IL
V_IH
V_IL
V_I/OH
V_I/OL
V_IH
V_IL
V_IH
V_IL
t_CSS
t_ALW
t_ADS
t_ADH
Address
t_RWD
t_RDS
t_DOD
Data out
t_RPW
t_CSH
t_DHR
Figure 25 - Intel Bus Interface Timing (Read Cycle)
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