MT9092 Datasheet, PDF (25/42 Pages) Mitel Networks Corporation – ISO2-CMOS ST-BUS™ FAMILY Digital Telephone with HDLC (HPhone-II)

MT9092
General Control Register
ADDRESS = 0Fh WRITE/READ VERIFY
RST
DATA
SEL
A/µ ^{Sign-Mag/ Rx}
CCITT A/µ
MIC Side NCT
A/µ A/µ
EN
Power Reset Value
0000 0000
7
6
5
4
3
2
1
0
RST
Active high reset. Performs the same function as PWRST but does not affect the microport or the watchdog circuits.
To remove this reset a PWRST must occur or this bit must be written low.
DATASEL
A/µ
Sign-mag/CCITT
RxA/µ
MICA/µ
SIDEA/µ
NCT EN
When high, the microport transmit and receive are performed on separate pins. DATA1 is receive while DATA2 is
transmit. When low, the microport conforms to Intel MCS-51 mode 0 specifications; DATA1 is a bi-directional
(transmit/receive) serial data pin while DATA2 is internally disconnected and tri-stated.
When high, A-Law (de)coding is selected. When low, µ-Law (de)coding is selected.
When high, sign-magnitude bit coding is selected, When low, true CCITT PCM coding is selected.
When high, the receiver driver nominal gain is set at -9.7 dB. When low this driver nominal gain is set at -12.3 dB.
When high, the transmit amplifier nominal gain is set at 15.4 dB. When low this amplifier nominal gain is set at 6.1
dB.
When high, the side-tone nominal gain is set at -18.8 dB. When low this nominal gain is set at -11 dB.
When high, the new call tone generator output from the DSP is selected as the source for the loudspeaker path.
When low, the CODEC output is selected for the loudspeaker path. Note that SPKR EN must also be set high for
new call tone to function.
ADDRESS 10h is RESERVED
Watchdog Register
-
-
-
W₄
W₃
W₂
W₁
W₀
7
6
5
4
3
2
1
0
WATCHDOG RESET WORD - XXX01010
ADDRESS = 11h WRITE
Power Reset Value
XXX0 1010
LCD Segment Enable Register 1
ADDRESS = 12h WRITE/READ VERIFY
SC₈ SC₇ SC₆ SC₅ SC₄ SC₃ SC₂ SC₁
Power Reset Value
0000 0000
7
6
5
4
3
2
1
0
Twelve segment control bits used for the LCD outputs. When high the respective segment is on. When low the respective segment is
off.
LCD Segment Enable Register 2
ADDRESS = 13h WRITE/READ VERIFY
-
-
-
-
SC₁₂ SC₁₁ SC₁₀ SC₉
Power Reset Value
XXXX 0000
7
6
5
4
3
2
1
0
Twelve segment control bits used for the LCD outputs. When high the respective segment is on. When low the respective segment is
off.
Note: Bits marked "-" are reserved bits and should be written with logic "0".
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