MT8910-1 Datasheet, PDF (23/26 Pages) Mitel Networks Corporation – CMOS ST-BUS™ FAMILY Digital Subscriber Line Interface Circuit

Preliminary Information
MT8910-1
DC Electrical Characteristics (continued) - Voltages are with respect to ground (V_SS) unless otherwise stated.
Characteristics
Sym Min Typ^‡ Max Units
Test Conditions
8
V_Bias Voltage
9
V_Ref Voltage
10
V_Bias and/or V_Ref load
11
Output High Voltage⁽¹⁾
12
Output Low Voltage ⁽¹⁾
13 ^O OSC2 Output High Voltage
U
14 _T OSC2 Output Low Voltage
15 ^P Differential Output Voltage
U
T
(L_out+ to L_out-)
16 _S Output Impedance
(L_out+, L_out-)
V_Bias
0.5AV_DD
V_Ref
-1.9
V_BL 1
V_OH 2.4
V_OL
0.4
V_OH
3.5
V_OL
1.5
V Relative to AV_SS
C_L=1 µF minimum to AV_SS
V Relative to V_Bias
C_L= 1µF minimum to AV_SS
MΩ (see Note 2)
V I_OH=10mA
V I_OL= 5.0mA
V I_OH=10µA
V I_OL=10µA
V_out
6.4
Z_out
0.5
V_pp R_L=40Ω
Measured by sourcing and
Ω sinking 10 mA. Line Driver
active.
17
Output Capacitance
(L_out+, L_out-)
C_o
50 pF (see Note 1)
18
High Impedance Leakage
I_OZ
10 µA
19
Supply Current
I_DD
65
mA Line Drivers active and
unloaded.
I_DD
10
mA Low Power Mode
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
(¹) except OSC2
Note 1) This is a specification on the maximum parallel capacitance to AC ground, connected directly to the pins. Higher
capacitance is acceptable when placed in series with resistor networks such as the line termination impedance.
2) Not production tested.
V_IH
C4b V_IL
V_IH
OSC2 _VIL
t_MCF
t_JC
t_OCH
t_JC
(See Note 3)
t_OCT
t_OCT
Figure 15 - External Clock Timing in LT Mode
AC Electrical Characteristics^†- External Clock Timing (Ref. Figure 15)
Characteristics
Sym Min Typ^‡ Max Units
Test Conditions
1 OSC2 Clock Frequency
1/t_MCF
10.24
MHz (see Notes 1, 2 & 3)
2 OSC2 Clock Duty Cycle
t_OCH/
45
50
55
%
t_MCF
3 OSC2 Clock Transition Time
t_OCT
10
ns
4 C4b Jitter (wrt OSC2)
t_JC
-15
+15 ns (see Note 3)
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Notes: 1) External clock tolerance of ±5 ppm in LT mode or ±50 ppm in NT mode is required.
2) Absolute jitter on OSC2 must be less than 2.0ns RMS in order to maximize performance.
3) In LT mode the C4b and OSC2 clocks must be externally frequency locked (i.e., f_OSC2 = 2.5 x f_C4b). The relative phase
between the clocks is not critical.
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