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MT8930C Datasheet, PDF (21/36 Pages) Mitel Networks Corporation – CMOS ST-BUS™ FAMILY Subscriber Network Interface Circuit Preliminary Information | |||
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Preliminary Information
MT8930C
BIT
NAME
DESCRIPTION
B7
EnDcoll A â1â will enable the D-channel collision interrupt.
A â0â will disable it. This bit is available only in TE mode.
B6 EnEOPD A â1â will enable the received End of Packet interrupt.
A â0â will disable it.
B5 EnTEOP A â1â will enable the transmit End of Packet interrupt.
A â0â will disable it.
B4
EnFA A â1â will enable the Frame Abort interrupt.
A â0â will disable it.
B3
EnTxFL A â1â will enable the Transmit FIFO Low interrupt.
A â0â will disable it.
B2 EnTxFun A â1â will enable the Transmit FIFO Underrun interrupt.
A â0â will disable it.
B1
EnRxFF A â1â will enable the Receive FIFO Full interrupt.
A â0â will disable it.
B0 EnRxFov A â1â will enable the Receive FIFO Overflow interrupt.
A â0â will disable it.
Table 9. HDLC Interrupt Mask Register (Write Add. 00100B)
BIT
B7
B6
B5
B4
B3
B2
B1
B0
Note 1:
NAME
DESCRIPTION
Dcoll(1)
EOPD(1)
TEOP(1)
FA(1)
TxFL(1)
TxFun(1)
A â1â indicates that a collision has been detected on the D-channel (i.e., received E-bit
does not match with transmitted D-bit). This bit is available only in TE mode and when the
HDLC transmitter is enabled. It always reads â0â in NT mode.
A â1âindicates that an end of packet has been detected on the HDLC receiver. This can be
in the form of a flag, an abort sequence or as an invalid packet.
A â1â indicates that the transmitter has finished sending the closing flag of the last packet in
the Tx FIFO, and the internal priority level is reduced from high to low.
A â1â indicates that the receiver has detected a frame abort sequence on the received data
stream.
A â1â indicates that the device has only four Bytes remaining in the Tx FIFO. This bit has
significance only when the Tx FIFO is being depleted and not when it is getting loaded.
A â1â indicates that the Tx FIFO is empty without being given the âend of packetâ indication.
The HDLC will transmit an abort sequence after encountering an underrun condition.
RxFF(1)
RxFov(1)
A â1â indicates that the HDLC controller has accumulated at least 15 bytes in the Rx
FIFO.
A â1â indicates that the Rx FIFO has overflown (i.e., an attempt to write to a full Rx FIFO).
The HDLC will always disable the receiver once the receive overflow has been detected.
The receiver will be re-enabled upon detection of the next flag.
Table 10. HDLC Interrupt Status Register (Read Add. 00100B)
All interrupts will be reset after a read to the HDLC Interrupt Status Register.
9-55
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