MT8980D-1 Datasheet, PDF (2/18 Pages) Mitel Networks Corporation – ISO-CMOS ST-BUS™ FAMILY Digital Switch

MT8980D
STi3
7
STi4
8
STi5
9
STi6 10
STi7
11
VDD
12
F0i 13
C4i 14
A0
15
A1
16
A2
17
39 STo3
38 STo4
37 STo5
36 STo6
35 STo7
34 VSS
33 D0
32 D1
31 D2
30 D3
29 D4
44 PIN PLCC
DTA ¹
STi0 ²
STi1 3
STi2 4
STi3 ⁵
STi4 6
STi5 7
STi6 8
STi7 9
VDD 10
F0i 11
C4i ¹²
A0 13
A1 14
A2 15
A3 16
A4 17
A5 18
DS 19
R/W 20
40 CSTo
39 ODE
38 STo0
37 STo1
36 STo2
35 STo3
34 STo4
33 STo5
32 STo6
31 STo7
30 VSS
29 D0
28 D1
27 D2
26 D3
25 D4
24 D5
23 D6
22 D7
21 _CS
40 PIN PLASTIC DIP
Pin Description
Figure 2 - Pin Connections
Pin #
Name
40 44
DIP PLCC
Description
1 2 DTA Data Acknowledgement (Open Drain Output). This is the data acknowledgement on the
microprocessor interface. This pin is pulled low to signal that the chip has processed the
data. A 909 Ω, 1/4W, resistor is recommended to be used as a pullup.
2-4 3-5 STi0- ST-BUS Input 0 to 2 (Inputs). These are the inputs for the 2048 kbit/s ST-BUS input
STi2 streams.
5-9 7-11 STi3- ST-BUS Input 3 to 7 (Inputs). These are the inputs for the 2048 kbit/s ST-BUS input
STi7 streams.
10 12 V_DD Power Input. Positive Supply.
11 13
F0i Framing 0-Type (Input). This is the input for the frame synchronization pulse for the
2048 kbit/s ST-BUS streams. A low on this input causes the internal counter to reset on
the next negative transition of C4i.
12 14 C4i 4.096 MHz Clock (Input). ST-BUS bit cell boundaries lie on the alternate falling edges of this
clock.
13- 15- A0-A2 Address 0 to 2 (Inputs). These are the inputs for the address lines on the microprocessor
15 17
interface.
16- 19- A3-A5 Address 3 to 5 (Inputs). These are the inputs for the address lines on the microprocessor
18 21
interface.
19 22
DS Data Strobe (Input). This is the input for the active high data strobe on the microprocessor
interface.
20 23 R/W Read or Write (Input). This is the input for the read/write signal on the microprocessor
interface - high for read, low for write.
21 24
CS Chip Select (Input). This is the input for the active low chip select on the microprocessor
interface
2-4