MT3170B Datasheet, PDF (2/8 Pages) Mitel Networks Corporation – Wide Dynamic Range DTMF Receiver

MT3170B/71B, MT3270B/71B, MT3370B/71B
MT3170B/71B
MT3270B/71B
INPUT ₁
PWDN 2
CLK 3
VSS 4
8 ^{VDD INPUT} 1
7
ESt/
DStD
OSC2
2
6 ACK OSC1 3
5 SD VSS 4
8 ^VDD
7
ESt/
DStD
6 ACK
5 SD
8 PIN PLASTIC DIP
NC
INPUT
PWDN
OSC2
NC
OSC1
NC
NC
VSS
MT3370B/71B
1
18 VDD
2
17 NC
3
16 NC
4
15 ESt/DStD
5
14 NC
6
13 ACK
7
12 NC
8
11 SD
9
10 NC
NC
NC
INPUT
PWDN
NC
OSC2
OSC1
VSS
NC
NC
18 PIN PLASTIC SOIC
MT3370B/71B
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
20 PIN SSOP
NC
NC
VDD
NC
ESt/DStD
NC
ACK
SD
NC
NC
Pin Description
337xB
2
4
6
Pin #
327xB
1
2
3
9
4
11
5
13
6
15
7
Figure 2 - Pin Connections
317xB
1
-
3
4
5
6
7
Name
Description
INPUT DTMF/CP Input. Input signal must be AC coupled via capacitor.
OSC2 Oscillator Output.
OSC1
(CLK)
Oscillator/Clock Input. This pin can either be driven by:
1) an external digital clock with defined input logic levels. OSC2
should be left open.
2) connecting a crystal or ceramic resonator between OSC1 and
OSC2 pins.
V_SS Ground. (0V)
SD Serial Data/Call Progress Output. This pin serves the dual function
of being the serial data output when clock pulses are applied after
validation of DTMF signal, and also indicates the cadence of call
progress input. As DTMF signal lies in the same frequency band as
call progress signal, this pin may toggle for DTMF input. The SD pin
is at logic low in powerdown state.
ACK
Acknowledge Pulse Input. After ESt or DStD is high, applying a
sequence of four pulses on this pin will then shift out four bits on the
SD pin, representing the decoded DTMF digit. The rising edge of the
first clock is used to latch the 4-bit data prior to shifting. This pin is
pulled down internally. The idle state of the ACK signal should be
low.
ESt Early Steering Output. A logic high on ESt indicates that a DTMF
(MT3x70B) signal is present. ESt is at logic low in powerdown state.
18
8
1,5,7,8,
-
10, 12,
14,16,
17
3
-
DStD ^{Delayed Steering Output. A logic high on DStD indicates that a}
(MT3x71B) valid DTMF digit has been detected. DStD is at logic low in
powerdown state.
8
V_DD Positive Power Supply (5V Typ.) Performance of the device can be
optimized by minimizing noise on the supply rails. Decoupling
capacitors across V_DD and V_SS are therefore recommended.
-
NC No Connection. Pin is unconnected internally.
2
PWDN Power Down Input. A logic high on this pin will power down the
device to reduce power consumption. This pin is pulled down
internally and can be left open if not used. ACK pin should be at logic
’0’ to power down device.
4-4