MT8952B-1 Datasheet, PDF (18/27 Pages) Mitel Networks Corporation – ISO-CMOS ST-BUS™ FAMILY HDLC Protocol Controller

MT8952B ISO-CMOS
AC Electrical Characteristics^† - Microprocessor Interface - (Figures 17 and 18)
Voltages are with respect to ground (V_SS) unless otherwise stated.
Characteristics
Sym Min Typ^‡ Max Units
Test Conditions
1 Delay between CS and E clock t_CSE
0
ns
2 Cycle time
t_CYC 205
ns
3 E Clock pulse width HIGH
t_EWH 145
ns
4 E Clock pulse width LOW
t_EWL
60
ns
5 Read/Write setup time
t_RWS 20
ns
6 Read/Write hold time
t_RWH 10
ns
7 Address setup time
t_AS
20
ns
8 Address hold time
t_AH
60
ns
9 Data setup time (write)
t_DSW 35
ns
10 Data hold time (write)
t_DHW 10
ns
11 E clock to valid data delay
t_DZL
t_DZH
145
ns
Test load circuit 1 (Fig. 26)
C_L=200pF
12 Data hold time (read)
t_DLZ
10
t_DHZ
60
ns Test load circuit 3 (Fig. 26)
†
‡
Timing
Typical
is over
figures
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CS
t_CSE
t_EWH
E clock initiates and
terminates the write cycle
E
t_EWL
t_r
t_f
t_CYC
CS
t_CSE
E
CS initiates and
terminates the write cycle
R/W
A0-A3
D0-D7
t_RWS
t_AS
t_AH
t_RWH
t_DSW
t_DHW
NOTE: The write cycle can be initiated either by the falling edge of CS or the rising edge of E clock whichever occurs last. Similarly
the cycle can be terminated by CS (rising edge) or E clock (falling edge) whichever occurs first. The timing relations are to be
referenced from the active edge initiating or terminating the cycle
Figure 17 - Timing Information for MPU Write
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