MT90826 Datasheet, PDF (14/30 Pages) Mitel Networks Corporation – Quad Digital Switch

MT90826 CMOS
Advanced Information
F0i
CLK
(16.384MHz)
Internal
master clock
at 32MHz
Offset Value
FEi Input
Frame Boundary
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
(FD[8:0] = 06_H, frame offset of six C32i clock cycles)
(FD9 = 0, sample at internal C32i low phase)
For 8Mb/s, 16Mb/s, 4&8Mb/s and 16&8Mb/s modes
F0i
CLK
(16.384MHz)
Internal
master clock
at 16 MHz
Offset Value
FEi Input
0
1
2
3
4
5
6
7
8
(FD[8:0] = 03_H, frame offset of three C16i clock cycles)
(FD9 = 0, sample at internal C16i low phase)
For 4Mb/s and 2&4Mb/s modes
F0i
CLK
(16.384MHz)
Internal
master clock
at 8MHz
Offset Value
FEi Input
14
0
1
2
3
4
(FD[8:0] = 02_H, frame offset of two C8i clock cycles)
(FD9 = 1, sample at internal C8i high phase)
For 2Mb/s mode
Figure 4 - Example for Frame Alignment Measurement