MT8982 Datasheet, PDF (13/14 Pages) Mitel Networks Corporation – ISO-CMOS ST-BUS™ FAMILY Small Digital Switch (MiniDX)

ISO-CMOS MT8982
AC Electrical Characteristics^† - TDM Bus (See Figures 13 and 14a, 14b). Voltages are with
respect to ground (V_SS) unless otherwise stated.
Characteristics
Sym Min Typ^‡ Max Units
Test Conditions
1 Frame Pulse Input Setup Time
2 Frame Pulse Input Hold Time
t_fs
10
t_fh
5
ns 4 meg mode
ns
5 cycles
3 Serial Output Delay;
t_sdaa
Active to Active
100
ns C_L=50pF
4 Serial Output Delay;
t_sdaz
Active to High Z
5 Serial Output Delay;
t_sdza
High Z to Active
200
ns C_L=50pF
R_L=1kΩ*
150
ns C_L=150pF
6 Serial Input Setup Time
t_ss
20
ns
7 Serial Input Hold Time
t_sh
10
ns
8 Frame Pulse Output Delay
t_fd
70
ns
9 ODE Low to Serial Out High Z
t_saz
125
ns C_L=50pF, R_L=1kΩ*
10 ODE High to Serial Out Active
t_sza
50
ns C_L=50pF, R_L=1kΩ
11 C4 Clock Pulse Width Low
t_c4l
25 100 209
ns t_c4 = 244 ns
12 C4 Clock Pulse Width High
t_c4h
35 100 219
ns t_c4 = 244 ns
13 C4 Clock Period
t_c4
150 244
ns
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* High impedance is measured by pulling to the appropriate rail with R_L, with timing corrected to cancel time taken to discharge C_L.
F0o (ST-BUS)
t_fd
t_fd
t_c4
t_c4l
t_c4h
C4i
F0o (GCI)
t_fd
t_fd
Figure 14a - TDM Bus Timing - F0o/Clock Timing
ODE
STo0-1
t_saz
t_sza
Figure 14b - ODE Timing
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