MT8980D Datasheet, PDF (12/14 Pages) Zarlink Semiconductor Inc – ISO-CMOS ST-BUS Family Digital Switch

MT8980D
AC Electrical Characteristics^† - Serial Streams (Figures 11, 14, 15 and 16)
Characteristics
Sym Min Typ^‡ Max Units
Test Conditions
1
STo0/7 Delay - Active to High Z t_SAZ 20
50
80
ns R_L=1 KΩ*, C_L=150 pF
2 O STo0/7 Delay - High Z to Active t_SZA 25
3
U
T
STo0/7 Delay - Active to Active
t_SAA
30
4 P STo0/7 Hold Time
5
U
T
Output Driver Enable Delay
t_SOH
25
t_OED
6 S External Control Hold Time
t_XCH
0
60 125
65 125
45
45 125
50
ns C_L=150 pF
ns C_L=150 pF
ns C_L=150 pF
ns R_L=1 KΩ*, C_L=150 pF
ns C_L=150 pF
7
External Control Delay
t_XCD
75 110 ns C_L=150 pF
8 _I Serial Input Setup Time
t_SIS
-40 -20 ns
9 ^N Serial Input Hold Time
t_SIH
90
ns
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* High Impedance is measured by pulling to the appropriate rail with R_L, with timing corrected to cancel time taken to discharge C_L.
Bit Cell Boundary
2.0V
C4i
0.8V
STo0 ^2.4V
to
STo7 0.4V
t_SOH
*
t_SAZ
STo0 2.4V
to
*
STo7 0.4V
STo0 2.4V
to
STo7 ^0.4V
2.4V
CSTo
0.4V
t_SZA
t_SOH
t_SAA
t_XCH
t_XCD
Figure 14 - Serial Outputs and External Control
2-14
2.0V
ODE
0.8V
STo0 ^2.4V
to
STo7 0.4V
*
t_OED
*
t_OED
Figure 15 - Output Driver Enable
2.0V
C4i
0.8V
STi0 2.0V
to
STi7 0.8V
Bit Cell Boundaries
t_SIH
t_SIS
Figure 16 - Serial Inputs