MT91L60 Datasheet, PDF (11/20 Pages) Mitel Networks Corporation – ISO2-CMOS 3 Volt Multi-Featured Codec (MFC)

Advance Information
MT91L60
the resynchronization circuitry activity and will not
affect operation since the bit cell period at 128 kb/s
and 256 kb/s is relatively large. There is a one frame
delay through the FDI circuit for asynchronous
operation. Refer to the specifications of Figures 12
& 13 for both synchronous and asynchronous SSI
timing.
PWRST/Software Reset (Rst)
While the MT91L60 is held in PWRST no device
control or functionality is possible. While in software
reset (Rst=1, address 03h) only the microport is
functional. Software reset can only be removed by
writing Rst logic low or by setting the PWRST pin.
After Power-up reset (PWRST) or software reset
(Rst) all control bits assume their default states;
µ-Law functionality, usually 0 dB programmable
gains as well as the device powered up in SSI mode
2048 kb/s operation with Dout tri-stated while there
is no strobe active on STB. If a valid strobe is
supplied to STB, then Dout will be active, during the
defined channel.
To attain complete power-down from a normal
operating condition, write PDFDI = 1 and PDDR = 1
(Control Register 1, address 03h) or put PWRST pin
low.
3V Multi-featured Codec Register Map
00
RxINC RxFG₂ RxFG₁ RxFG₀ TxINC TxFG₂ TxFG₁ TxFG₀ Gain Control
Register 1
01
-
-
-
-
-
STG₂
STG₁
STG₀ Gain Control
Register 2
02
-
-
-
-
-
-
-
DrGain Path Control
03
PDFDI PDDR
RST
-
T_xMute R_xMute T_xBsel R_xBsel
Control
Register 1
04
CEN
DEN
D8
A/µ
Smag/
CSL₂
CSL₁
CSL₀
Control
ITU-T
Register 2
05
C₇
C₆
C₅
C₄
C₃
C₂
C₁
C₀
C-Channel
Register
06
D₇
D₆
D₅
D₄
D₃
D₂
D₁
D₀
D-Channel
Register
07
-
-
-
-
PCM/ loopen
-
-
Loop Back
ANALOG
7-117