MT90810 Datasheet, PDF (11/34 Pages) Mitel Networks Corporation – CMOS Flexible MVIP Interface Circuit

Preliminary Information
MT90810
memory and auto increment/decrement mode is
written to the AMR. Finally, the write operation is
performed when data is written to the Indirect Data
Register(IDR). Similarly, to perform a read operation
from an indirect location, the LAR and AMR must be
initialized and then the data can be read from the
IDR.
Data memory can be read and written by the
microprocessor. This is accomplished by first
initializing the LAR and AMR register to select data
memory and then either reading from or writing to
the Indirect Data Register.
Connection memory can be read and written by the
microprocessor. This is accomplished by first
initializing the LAR and AMR register to select high
or low connection memory and then either reading
from or writing to the IDR.
The indirect address can be programmed to auto-
increment after reads or writes to the indirect data
register by setting bits 6 and 7 in the AMR
accordingly. The auto-increment occurs only when
the indirect address register points to either data
memory or the high byte of connection memory.
If auto-increment on read/write is enabled, and
connection memory is selected, then consecutive
reads/writes to the IDR will toggle between selection
of low to high then back to low byte of connection
memory and continue on toggling until the reads/
writes to IDR stop. Note that when reading/writing
connection memory with auto increment disabled,
the reads/writes to IDR will toggle from low to high
byte connection memory once only.
Using the auto-increment feature, the connection
memory can be quickly initialized by resetting the
LAR and initializing the AMR for auto-increment on
write with connection memory low byte selected.
Writing a stream of bytes to IDR will then fill
connection memory. The first byte written to the IDR
will go to the low byte of the first connection memory
location. The memory space selection will be
automatically toggled to select connection memory
high. The second byte written to the IDR will then be
written to connection memory high of the first
connection memory location. The memory space will
automatically toggle back to the low byte connection
memory and the address pointer will be incremented
to prepare for writing to the next location in
connection memory. Similarly, the contents of
connection memory can also be read back quickly by
setting the auto-increment on read bit of AMR and
reading from the IDR continuously.
Writing to a data memory of connection memory
when the address register contains an indirect RAM
address of greater than 383 will cause unpredictable
results.
DMA Interface
The DMA interface to the FMIC is accessible only
when the microprocessor interface is in INTEL mode.
All 128 local channels can be DMA’ed out to/in from
external memory. MVIP channels can be DMA’ed by
switching to local channels.
The DMA_EN bit in the FMIC Control/Status register
enables DMA mode. This bit should be set only after
the desired local channels have been enabled for
DMA. The DMA_EN bit does not take effect until
after the beginning of the next MVIP frame. This
assures that when the DMA transactions begin, that
they begin on a frame boundary.
An individual local channel is enabled for DMA by
setting the CE bit in connection memory high for that
channel. When a channel is enabled for DMA, both
input and output are enabled for DMA. The local
output data is also driven out on the programmed
serial output stream. It is not possible to enable input
without output or vice versa. If channels in time slot
0 are enabled for DMA, there will be no DMA
requests for those channels in the first frame after
DMA is enabled. Instead, setup and preparation for
the DMA will occur in that first frame, in the timeslot
preceding. DMA transfer will actually occur in the
second frame after DMA is enabled. It is, therefore,
recommended that channels in time slot 0 not be
enabled for DMA.
The DMA signals DREQ[1] and DACK[1] control
transfers for DMA reads from the FMIC while
DREQ[0] and DACK[0] control transfers for DMA
writes to the FMIC. For every 2Mb/s timeslot where a
channel is enabled for DMA, the FMIC will assert
DREQ and wait for a DACK from an external
controller. Upon receiving the acknowledgement,
DACK, it would proceed with one DMA burst transfer.
DMA read requests always occur at the beginning of
the 2Mb/s time slot during which, all channels
enabled for DMA in the timeslot will be DMA’ed out in
a burst, onto the local serial data stream. One burst
implies one DREQ cycle, whereby DREQ is held low
for the duration of the transfer. The maximum
number of 8 bit channels that can be DMA’ed out
during one burst is 4, since, regardless of the serial
interface mode, there can be only four 8 bit channels
per 2Mb/s time slot, whether it be one channel per
stream (on 4 streams) at 2Mb/s, 2 channels per
stream (on 2 streams) at 4Mb/s or 4 channels all on
one stream at 8Mb/s.
DMA write requests occur at the end of the 2Mb/s
time slot during which, all channels enabled for DMA
in the timeslot will be DMA’ed from the local serial
data stream. DMA write requests can also occur in
bursts of up to four 8 bit channels. The data for write
requests is actually staggered by one DMA request
for each stream. This means that the data written
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