MT89L80 Datasheet, PDF (10/15 Pages) Mitel Networks Corporation – CMOS ST-BUS™ FAMILY Digital Switch

MT89L80
Advance Information
AC Electrical Characteristics^† - Clock Timing (Figures 9 and 10)
Characteristics
Sym Min Typ^‡ Max Units
Test Conditions
1
Clock Period*
t_CLK 220 244 300
ns
2 _I Clock Width High
3 N Clock Width Low
4
P
U
Clock Transition Time
5 T Frame Pulse SetupTime
6 ^S Frame Pulse Hold Time
t_CH
85 122 150 ns
t_CL
85 122 150 ns
t_CTT
10
ns
t_FPS
10
190 ns
t_FPH
10
190 ns
7
Frame Pulse Width
t_FPW
244
ns
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* Contents of Connection Memory are not lost if the clock stops, however, ST-BUS outputs go into the high impedance state.
NB: Frame Pulse is repeated every 512 cycles of C4i.
C4i
F0i
BIT
CELLS
Channel 31
Bit o
Channel 0
Bit 7
Figure 9- Frame Alignment
V_HM
C4i
V_LM
F0i ^VHM
V_LM
2-12
t_CLK
t_CL
t_CTT
t_FPH
t_CHL
t_FPS
t_CTT
t_FPH
t_FPW
Figure 10 - Clock Timing
t_CH
t_FPS