MT8941B Datasheet, PDF (10/22 Pages) Mitel Networks Corporation – CMOS ST-BUS™ FAMILY Advanced T1/CEPT Digital Trunk PLL

MT8941B CMOS
Besides the improved jitter performance, the
MT8941B differs from the MT8940 in three other
areas:
1. Input pins on the MT8941B do not incorporate
internal pull-up or pull-down resistors. In
addition, the output configuration of the
bidirectional C8Kb pin has been converted from
an open drain output to a Totem-pole output.
2. The MT8941B includes a no-correction window
to filter out low frequency jitter and wander as
illustrated in Figure 4. Consequently, there is no
constant phase relationship between reference
signal F0i of DPLL # 1 or C8Kb of DPLL #2 and
the output clocks of DPLL #1 or DPLL #2.
Figure 4 shows the new phase relationship
between C8Kb and the DPLL #2 output clocks.
Figure 8 illustrates an application where the
MT8941B cannot replace the MT8940 and
suggests an alternative solution.
3. The MT8941B must be reset after power-up in
order to guarantee proper operation, which is not
the case for the MT8940.
4. For the MT8941B, DPLL #2 locks to the falling
edge of the C8Kb reference signal. DPLL#2 of
the MT8940 locks on to the rising edge of C8Kb.
5. While the MT8940 is available only in a 24 pin
plastic DIP, the MT8941B has an additional 28
pin PLCC package option.
Applications
The following figures illustrates how the MT8941B
can be used in a minimum component count
approach in providing the timing and synchro-
nization signals for the Mitel T1 or CEPT interfaces,
and the ST-BUS. The hardware selectable modes
and the independent control over each PLL adds
flexibility to the interface circuits. It can be easily
reconfigured to provide the timing and control signals
for both the master and slave ends of the link.
Synchronization and Timing Signals for the T1
Transmission Link
Figures 9 and 10 show examples of how to generate
the timing signals for the master and slave ends of a
T1 link. At the master end of the link (Figure 9),
DPLL #2 is the source of the ST-BUS signals derived
from the crystal clock. The frame pulse output is
looped back to DPLL #1 (in NORMAL mode), which
locks to it to generate the T1 line clock. The timing
relationship between the 1.544 MHz T1 clock and the
2.048 MHz ST-BUS clock meets the requirements of
the MH89760/760B. The crystal clock at 12.352
MHz is used by DPLL #1 to generate the 1.544 MHz
clock, while DPLL #2 (in FREE-RUN mode) uses the
16.384 MHz crystal oscillator to generate the ST-
BUS clocks for system timing. The generated ST-
BUS signals can be used to synchronize the system
and the switching equipment at the master end.
Crystal Clock
(12.352 MHz)
Crystal Clock
(16.384 MHz)
MT8941B
MT8980/81
MS0
MS1
MS2
MS3
F0i
C12i
EN_CV
C8Kb
C16i
EN_C4o
EN_C2o
V_DD
CVb
C4b
C2o
F0b
V_{SS RST}
MH89760B
C1.5i
C2i
F0i
DSTi
DSTo
CSTi
CSTo
TxT
TxR
RxT
RxR
TRANSMIT
RECEIVE
ST-BUS
SWITCH
T1
LINK
(1.544 Mbps)
Mode of Operation for the MT8941B
V_DD
DPLL #1 - NORMAL (MS0 = X; MS1 = 0)
C
R
DPLL #2 - FREE-RUN (MS0=1; MS2=1; MS3=1)
Figure 9 - Synchronization at the Master End of the T1 Transmission Link
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