VP2614 Datasheet, PDF (1/12 Pages) Mitel Networks Corporation – H.261 Video De-Multiplexer

VP2614
VP2614
H.261 Video De-Multiplexer
Supersedes version in June 1995 Digital Video & DSP IC Handbook, HB3923-2
DS3735 - 3.2 October 1996
FEATURES
s Fully integrated H.261 video de-multiplexer
s Inputs an H.261 bitstream. Outputs error corrected run
length coded coefficients.
s Interfaces directly to the VP2615 H.261 decoder
s Extracts side information and status for transfer to a
System Controller
s User definable system level options for proprietary ap-
plications
s Average input rates between 40 Kbit /sec and 2Mbit /
sec. Maximum peak input rates of 4 Mbit / sec.
s 100 pin quad flatpack
ASSOCIATED PRODUCTS
s VP2611 H.261 Encoder
s VP2612 H.261 Video Multiplexer
s VP2615 H.261 Decoder
s VP520S CIF / QCIF Converter
s VP510 Colour Space Converter
DESCRIPTION
The VP2614 Video De-Multiplexer forms part of the Mitel
Semiconductor chip set for video conferencing, video te-
lephony, and multimedia applications. It extracts video pa-
rameters and run length coded DCT coefficients from an
H.261 bitstream. Elements of the data which have been
variable length coded according to the specification are de-
coded within the device. It produces tagged data, aligned to a
macroblock timing structure, in the format needed by the
VP2615 Decoder. Side information and status bits are sepa-
rately made available for the system controller.
The VP2614 will accept data up to a peak rate of 4 Mbits
per second, but with an average rate up to 2 Mbits per second.
The bursty nature of the input, together with the fact that each
coded picture does not use the same number of bits, requires
the provision of a received data buffer. Since the VP2615
Decoder accepts macroblock data as it becomes available, it
is not necessary to provide storage for a complete coded
picture. Worst case analysis has shown that a buffer size of
256K bits is adequate in practice for bit rates up to 2Mb/sec.
The incoming sequence is coded with a strict syntax, and
the VP2614 must identify and align with this sequence before
correct decoding is possible. Storage for this alignment is
contained within the external buffer. The device monitors that
lock is always valid, and reports to the system controller. Error
correction bits are ignored.
HD7:0 HA3:0 CEN WR
RD VMUX ERROR VMUX EVENT
RECEIVE
BUFFER
32K X 8
DATA
STROBE
DATA
VALID
NOT
READY
CNTRL
DATA
ADDR
FRAME
ALIGNMENT
HOST INTERFACE
SIDE INFORMATION
VALIDITY
CHECK
VARIABLE
LENGTH
DECODE
VP2615
INTER
FACE
BUFFER
INTERFACE
Fig 1 : Simplified Block Diagram
VP2614
PMD
2:0
D7:0
DM3:0
DCLK
1