SP5669 Datasheet, PDF (1/15 Pages) Mitel Networks Corporation – 2.7GHz I2C Bus Controlled Synthesiser

SP5669
2.7GHz I²C Bus Controlled Synthesiser
Preliminary Information
DS4852 -
Issue 2.1
May 1999
Features
q Complete 2.7GHz single chip system
q Compatible with UK DTT offset requirements
q Optimised for low phase noise
q Selectable divide by two prescaler
q Selectable reference division ratio
q Selectable reference/comparison frequency output
q Selectable charge pump current
q Four selectable I²C bus address
q 5–level ADC
q Pin compatible with the SP5658 3–wire bus
controlled synthesiser and SP5659 I²C bus
synthesiser and SP5659 I²C bus synthesiser
ESD protection; (Normal ESD handling
procedures should be observed)
Applications
q Complete 2.7GHz single chip system
q Optimised for low phase noise
Ordering Information
SP5669/KG/MP1S (Tubes)
SP5669/KG/MP1T (Tape and reel)
The comparison frequency is obtained either from an
on–chip crystal controlled oscillator, or from an external
source. The oscillator frequency F_ref or the comparison
frequency F may be switched to the REF/COMP
comp
output. This feature is ideally suited to providing the
reference frequency for a second synthesiser such as in
a double conversion tuner (see Fig. 8).
The synthesiser is controlled via an I ² C bus, and
responds to one of four programmable addresses which
are selected by applying a specific voltage to the
‘address’ input. This feature enables two or more
synthesisers to be used in a system.
Description
The SP5669 is a single chip frequency synthesiser
designed for tuning systems up to 2.7GHz and offers
step size compatible with DTT offset requirements.
The RF preamplifier drives a divide by two prescaler
which can be disabled for applications up to 2GHz,
allowing direct interfacing with the programmable
divider so enabling a step size equal to the comparison
frequency. For applications up to 2.7GHz the divide by
two is enabled, giving a step size of twice the
comparison frequency.
The device contains four switching ports P0–P3 and a
5–level ADC. The output of the ADC can be read via the
I² C
bus.
The device also contains a varactor line disable and
chargepump disable facility.