MT9300 Datasheet, PDF (1/29 Pages) Mitel Networks Corporation – Multi-Channel Voice Echo Canceller

Features
• Independent multiple channels echo
cancellation; from 32 channels of 64ms to 16
channels of 128ms with the ability to mix
channels at 128ms or 64ms in any combination
• Independent Power Down mode for each group
of 2 channels for power management
• Conforms to ITU-T G.165 and G.168
Recommendations
• Field proven, high quality performance
• Compatible to ST-BUS and GCI interface at
2Mb/s serial PCM
• PCM coding, µ/A-Law ITU-T G.711 or sign
magnitude
• Per channel Fax/Modem G.164 2100Hz or
G.165 2100Hz phase reversal Tone Disable
• Per channel echo canceller parameters control
• Transparent data transfer and mute
• Non-Linear processor with high quality
subjective performance
• Protection against narrow band signal
divergence
• Offset nulling of all PCM channels
• 10 MHz or 20 MHz master clock operation
• 3.3 Volts operation with 5-Volt tolerant inputs
• No external memory required
• Non-multiplexed microprocessor interface
• IEEE-1149.1 (JTAG) Test Access Port
MT9300
Multi-Channel Voice Echo Canceller
Advance Information
DS5030
ISSUE 2
May 1999
Ordering Information
MT9300AL
160-Pin MQFP
-40°C to +85°C
Applications
• Voice over IP network gateways
• Voice over ATM, Frame Relay
• T1/E1/J1 multichannel echo cancellation
• Wireless base stations
• Echo Canceller pools
• DCME, satellite and multiplexer systems
Description
The MT9300 Voice Echo Canceller implements a
cost effective solution for telephony voice-band echo
cancellation conforming to ITU-T G.168
requirements. The MT9300 architecture contains 16
groups of two echo cancellers (ECA and ECB) which
can be configured to provide two channels of 64
milliseconds or one channel of 128 milliseconds
echo cancellation. This provides 32 channels of 64
milliseconds to 16 channels of 128 milliseconds echo
cancellation or any combination of the two
configurations. The MT9300 supports ITU-T G.165
and G.164 tone disable requirements.
Rin
Sin
MCLK
Fsel
C4i
F0i
V_DD V_SS
Serial
to
Parallel
PLL
Timing
Unit
ODE
Echo Canceller Pool
Group 0 Group 1 Group 2 Group 3
ECA/ECB ECA/ECB ECA/ECB ECA/ECB
Group 4 Group 5 Group 6 Group 7
ECA/ECB ECA/ECB ECA/ECB ECA/ECB
Group 8 Group 9 Group 10 Group 11
ECA/ECB ECA/ECB ECA/ECB ECA/ECB
Group 12 Group 13 Group 14 Group 15
ECA/ECB ECA/ECB ECA/ECB ECA/ECB
Parallel
to
Serial
Note:
Refer to Figure 3
for Echo Canceller
block diagram
Microprocessor Interface
Test Port
Rout
Sout
IC0
RESET
DS CS R/W A10-A0 DTA D7-D0 IRQ TMS TDI TDO TCK TRST
Figure 1 - Functional Block Diagram
1