MT9123 Datasheet, PDF (1/32 Pages) Mitel Networks Corporation – CMOS Dual Voice Echo Canceller

CMOS MT9123
®
Dual Voice Echo Canceller
Preliminary Information
Features
• Dual channel 64ms or single channel 128ms
echo cancellation
• Conforms to ITU-T G.165 requirements
• Narrow-band signal detection
• Programmable double-talk detection threshold
• Non-linear processor with adaptive suppression
threshold and comfort noise insertion
• Offset nulling of all PCM channels
• Controllerless mode or Controller mode with
serial interface
• ST-BUS or variable-rate SSI PCM interfaces
• Selectable µ/A-Law ITU-T G.711; µ/A-Law Sign
Mag; linear 2’s complement
• Per channel selectable 12 dB attenuator
• Transparent data transfer and mute option
• 19.2 MHz master clock operation
Applications
• Wireless Telephony
• Trunk echo cancellers
ISSUE 1
October 1996
Ordering Information
MT9123AP 28 Pin PLCC
MT9123AE 28 Pin PDIP
-40 °C to + 85 °C
Description
The MT9123 Voice Echo Canceller implements a
cost effective solution for telephony voice-band echo
cancellation conforming to ITU-T G.165
requirements. The MT9123 architecture contains two
echo cancellers which can be configured to provide
dual channel 64 millisecond echo cancellation or
single channel 128 millisecond echo cancellation.
The MT9123 operates in two major modes:
Controller or Controllerless. Controller mode allows
access to an array of features for customizing the
MT9123 operation. Controllerless mode is for
applications where default register settings are
sufficient.
Sin
Rout
ENA2
ENB2
NLP
LAW
FORMAT
IC3
IC4
Linear/
µ/A-Law
Programmable
Bypass
Offset
Null
+
-
Non-Linear
Processor
Linear/
µ/A-Law
Microprocessor
Interface
Double-Talk
Detector
Narrow-Band
Detector
Linear/
µ/A-Law
12dB
Attenuator
Offset
Null
Linear/
µ/A-Law
Echo Canceller A
Echo Canceller B
Sout
Rin
ENA1
ENB1
CONFIG1
CONFIG2
S1/DATA1
S2/DATA2
S3/CS
S4/SCLK
IC1 IC2
VDD VSS
PWRDN
F0od
F0i
BCLK/C4i MCLK
Figure 1 - Functional Block Diagram
8-45