MT90840 Datasheet, PDF (1/4 Pages) Mitel Networks Corporation – Distributed Hyperchannel Switch

®
MT90840
Distributed Hyperchannel Switch
Advance Information
Features
• Time-slot interchange function between 8 pairs
of ST-BUS/GCI/MVIP streams (512 channels)
and a Parallel Data Port (PDP)
• Supports star, point to point connections and
unidirectional or bidirectional ring topologies for
distributed systems
• Input to Output Bypass function with minimum
delay for shared ring applications
• Provides an internal latency adjustment buffer
for ring applications
• Parallel port data rates up to 19.44Mbyte/s
• Programmable data rates on the serial port side
(2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s)
• Unidirectional Parallel switching mode for up to
2430 channels non-blocking
• Per-channel direction control on the serial port
side
• Per-channel message mode and high-
impedance control on both parallel and serial
port sides
• 8-bit multiplexed port compatible with Intel and
Motorola microcontrollers
• Guarantees frame integrity when switching
wideband channels such as ISDN H0 channel
• Provides external control lines allowing the fast
parallel interface to be shared with other
devices
C4OUT
C4REF1
C4REF2
FO
SERIAL PORT TIMING
CONTROL
ISSUE 1
June 1995
Ordering Information
MT90840AK 100 Pin PQFP
MT90840AP 84 Pin PLCC
-40°C to 85°C
• Special diagnostic alarm functions for statistical
analysis
• JTAG boundary scan
Applications
• Bridging ST-BUS/MVIP buses to high speed
Time Division Multiplex backplanes at SONET
rates (STS-1/3)
• High speed isochronous backbones for
distributed PBX and Local Area Network
systems
• Switch platforms of up to 2430 channels with
guaranteed frame integrity for wideband
channels
• Serial bus control and monitoring
• Data multiplexer
• High speed communications interface
• Isochronous switching/multiplexing to support
IEEE 802.9 standards
PARALLEL PORT TIMING
CONTROL
PPFRo
PCKT
PPFRi
PCKR
Serial
Data
Port
DSo[0:7]
D Si [0:7]
TCK
TMS
TDI
TDO
RECEIVE PATH
RECEIVE
DATA & CONN
LATENCY
MEMORIES
BUFFER
S-P
&
P-S
JTAG
TRANSMIT PATH
DATA & CONN
MEMORIES
Microprocessor Interface
PARALLEL
PORT
INTERFACE
EXTERNAL
CONTROL
P Di 0-7
PDo0-7
Parallel
Data
Port
CT0
CT1
CT2
CT3
RESET _AD[0:7] ALE WR/ RD/ CS DTACK INT
R/W DS
Figure 1 - Functional Block Diagram
2-189