MT90820 Datasheet, PDF (1/10 Pages) Mitel Networks Corporation – CMOS ST-BUS™ FAMILY Large Digital Switch (LDX)

CMOS ST-BUS™ FAMILY MT90820
®
Large Digital Switch (LDX)
Advance Information
Features
• 2,048 channel non-blocking switch
• Maintains frame integrity on concatenated
channels.
• Per-channel selection of minimum or constant
throughput delay
• Serial streams at 2.048, 4.096 or 8.192Mb/s
• Frame offset delay measurement
• Programmable frame delay offset
• Per-channel three-state control
• Per-channel message mode
• Control interface compatible to Intel/Motorola
CPUs
• Block programming feature for connection
memory
• ST-BUS/MVIP and GCI interfaces
• Test Port compatible to IEEE-1149.1 standard
Applications
• Medium and large switching platforms
• C.O. switches
• CTI application
• Voice/data multiplexer
• Digital cross connects
• ST-BUS/HMVIP interface functions
ISSUE 1
Ordering Information
May 1995
MT90820AP
MT90820AL
84 Pin PLCC
100 Pin QFP
Description
-40 to +85°C
The Large Digital Switch (LDX) is an advanced
digital switch allowing the users to build up to 2048
channel non-blocking switch. The serial interface can
be at 2, 4 or 8 Mb/s compatible to ST-BUS/MVIP/
HMVIP or GCI standards. The LDX can be
programmed to provide either minimum or constant
throughput delay on all its channels. The device also
features three-state control and message mode on
per-channel basis.
To manage the problem of line delays, each input
stream can have an individually programmed input
frame offset delay. The offset delay can be calibrated
with a dedicated frame measurement facility inside
the device.
V_DD V_SS
TMS TDI TDO TCK TRSTB TEST RESETB
ODE
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STi8
STi9
STi10
STi11
STi12
STi13
STi14
STi15
Serial
to
Parallel
Converter
Timing
Unit
Test Port
Multiple Buffer
Data Memory
Internal
Registers
Output
MUX
Connection
Memory
Parallel
to
Serial
Converter
Microprocessor Interface
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
STo8
STo9
STo10
STo11
STo12
STo13
STo14
STo15
CLK FRM FE/ HMVIP
HCLK
AS/
ALE
IM
DS
RD
CS
R/W
WR
A7-A0 DTA D15-D8/ CSTo
AD7-AD0
Figure 1 - Functional Block Diagram
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