MT9075B Datasheet, PDF (1/78 Pages) Mitel Networks Corporation – E1 Single Chip Transceiver

Features
• Combined PCM 30 framer, Line Interface Unit
(LIU) and link controllers in a 68 pin PLCC or
100 pin MQFP package
• Selectable bit rate data link access with
optional S_a bits HDLC controller (HDLC0) and
channel 16 HDLC controller (HDLC1)
• LIU dynamic range of 20 dB
• Enhanced performance monitoring and
programmable error insertion functions
• Low jitter DPLL for clock generation
• Operating under synchronized or free run mode
• Two-frame receive elastic buffer with controlled
slip direction indication
• Selectable transmit or receive jitter attenuator
• Intel or Motorola non-multiplexed parallel
microprocessor interface
• CRC-4 updating algorithm for intermediate path
points of a message-based data link application
• ST-BUS/GCI 2.048 Mbit/s backplane bus for
both data and signalling
Applications
• E1 add/drop multiplexers and channel banks
• CO and PBX equipment interfaces
• Primary Rate ISDN nodes
• Digital Cross-connect Systems (DCS)
MT9075B
E1 Single Chip Transceiver
Preliminary Information
ISSUE 1
March 1998
Ordering Information
MT9075BP 68Pin PLCC
MT9075BL 100 Pin MQFP
-40°C to 85°C
Description
The MT9075B is a single chip device which
integrates an advanced PCM 30 framer with a Line
Interface Unit (LIU).
The framer interfaces to a 2.048 Mbit/s backplane
and provides selectable rate data link access with
optional HDLC controllers for S_a bits and channel 16.
The LIU interfaces the framer functions to the PCM
30 transformer-isolated four wire line.
The MT9075B meets or supports the latest ITU-T
Recommendations including G.703, G.704, G.706,
G.732, G.775, G.796, G.823 for PCM 30, and I.431
for ISDN primary rate. It also meets or supports ETSI
ETS 300 011, ETS 300 166 and ETS 300 233 as well
as BS 6450.
DSTi
CSTi
Tdi
Tdo
Tms
Tclk
Trst
INT/MOT
IRQ
D7~D0
AC4
~AC0
R/W/WR
CS
DS/RD
DSTo
CSTo
TxDL TxDLCLK TxMF
TAIS
ST-BUS
Interface
Transmit Framing, Error and
Test Signal Generation
Line
Driver
ST Loop
PL Loop
Data Link,
HDLC0,
HDLC1
National
Bit Buffer
CAS
Buffer
Jitter Attenuator
& Clock Control
DG Loop
ST-BUS
Interface
Receive Framing, Performance Monitoring,
Alarm Detection, 2 Frame Slip Buffer
RxDLCLK RxDL RxMF
LOS
RxFP/Rx64kCK E2o F0b C4b
Figure 1 - Functional Block Diagram
TTIP
TRING
MS/FR
M/S
OSC1
OSC2
RTIP
RRING
1