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MT9042C Datasheet, PDF (1/28 Pages) Mitel Networks Corporation – Multitrunk System Synchronizer | |||
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Features
⢠Meets jitter requirements for: AT&T TR62411
Stratum 3, 4 and Stratum 4 Enhanced for DS1
interfaces; and for ETSI ETS 300 011, TBR 4,
TBR 12 and TBR 13 for E1 interfaces
⢠Provides C1.5, C3, C2, C4, C8 and C16 output
clock signals
⢠Provides 8kHz ST-BUS framing signals
⢠Selectable 1.544MHz, 2.048MHz or 8kHz input
reference signals
⢠Accepts reference inputs from two independent
sources
⢠Provides bit error free reference switching -
meets phase slope and MTIE requirements
⢠Operates in either Normal, Holdover and
Freerun modes
Applications
⢠Synchronization and timing control for
multitrunk T1 and E1 systems
⢠ST-BUS clock and frame pulse sources
⢠Primary Trunk Rate Converters
MT9042C
Multitrunk System Synchronizer
Advance Information
DS5144
ISSUE 2
September 1999
Ordering Information
MT9042CP 28 Pin PLCC
-40°C to +85°C
Description
The MT9042C Multitrunk System Synchronizer
contains a digital phase-locked loop (DPLL), which
provides timing and synchronization signals for
multitrunk T1 and E1 primary rate transmission links.
The MT9042C generates ST-BUS clock and framing
signals that are phase locked to either a 2.048MHz,
1.544MHz, or 8kHz input reference.
The MT9042C is compliant with AT&T TR62411
Stratum 3, 4 and 4 Enhanced, and ETSI ETS 300
011. It will meet the jitter tolerance, jitter transfer,
intrinsic jitter, frequency accuracy, holdover
accuracy, capture range, phase slope and MTIE
requirements for these speciï¬cations.
OSCi
OSCo
PRI
SEC
RSEL
LOS1
LOS2
TRST
VDD VSS
Master
Clock
TIE
Corrector
Circuit
Virtual
Refer-
ence
DPLL
Reference
Select
MUX
Reference
Select
Selected
Refer-
ence
TIE
Corrector
Enable
Automatic/Manual
Control State Machine
State
Select
State
Select
Input
Impairment
Monitor
Guard Time
Circuit
Output
Interface
Circuit
Feedback
Frequency
Select
MUX
MS1 MS2 RST
GTo
GTi
FS1
FS2
Figure 1 - Functional Block Diagram
C1.5o
C3o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
1
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