MT9042 Datasheet, PDF (1/16 Pages) Mitel Networks Corporation – Global Digital Trunk Synchronizer

MT9042
®
Global Digital Trunk Synchronizer
Preliminary Information
Features
• Provides T1 and E1 clocks, and ST-BUS/GCI
framing signals locked to an input reference of
either 8 kHz (frame pulse), 1.544 MHz (T1), or
2.048 MHz (E1)
• Meets AT & T TR62411 and ETSI ETS 300 011
specifications for a 1.544 MHz (T1), or
2.048 MHz (E1) input reference
• Provides Time Interval Error (TIE) correction to
suppress input reference rearrangement
transients
• Typical unfiltered intrinsic output jitter is
0.013 UI peak-to-peak
• Jitter attenuation of 15 dB @ 10 Hz,
34 dB @ 100 Hz and 50 dB @ 5 to 40 kHz
• Low power CMOS technology
Applications
• Synchronization and timing control for T1 and
E1 digital transmission links
• ST-BUS clock and frame pulse sources
• Primary Trunk Rate Converters
ISSUE 1
Ordering Information
MT9042AP 28 Pin PLCC
-40^°C to +85^°C
June 1994
Description
The MT9042 is a digital phase-locked loop (PLL)
designed to provide timing and synchronization
signals for T1 and E1 primary rate transmission links
that are compatible with ST-BUS/GCI frame
alignment timing requirements. The PLL outputs can
be synchronized to either a 2.048 MHz, 1.544 MHz,
or 8 kHz reference. The T1 and E1 outputs are fully
compliant with AT & T TR62411 (ACCUNET^® T1.5)
and ETSI ETS 300 011 intrinsic jitter and jitter
transfer specifications, respectively, when
synchronized to primary reference input clock rates
of either 1.544 MHz or 2.048 MHz.
The PLL also provides additional high speed output
clocks at rates of 3.088 MHz, 4.096 MHz, 8.192
MHz, and 16.384 MHz for backplane synchro-
nization.
VDD VSS
RST
PRI
SEC
Reference
Select
MUX
TRST
MCLKo
MCLKi
TIE
PLL
Corrector
Interface
Circuit
RSEL
LOSS1
LOSS2
Automatic State
Machine
Divider
C3
C1.5
C16
C8
C4
C2
F0o
FP8-STB
FP8-GCI
GTo GTi MS1 MS2
FSEL1 FSEL2
Figure 1 - Functional Block Diagram
3-97