MT90210 Datasheet, PDF (1/27 Pages) Mitel Networks Corporation – Multi-Rate Parallel Access Circuit

MT90210
Multi-Rate Parallel Access Circuit
Preliminary Information
Features
• Parallel-to-serial and serial-to-parallel
conversion of up to 1536 full duplex channels or
3072 time-slots
• Serial port data rates selectable between 2.048,
4.096 or 8.192 Mb/s
• Provides a mechanism for a double buffer
function to be implemented in external memory
• 24 serial I/O lines programmable in different
modes: 12 in/12 out at 8.192 Mb/s (1536 full
duplex channels) or 24 bidirectional line modes
for 2.048 and 4.096 Mb/s
• Provides a bidirectional 8-bit parallel port
operating at 16.384 or 32.768 MByte/s for direct
interface to external memory (dual port)
• Provides an external 13-bit output address bus
for direct connection with an 8K-position dual
port memory
• JTAG boundary scan
Applications
• Fast access to ST-BUS, SCSA, MVIP, and
H-MVIP serial backplanes
• Voice processing cards for Computer Telephony
Integration (CTI)
• Video and teleconferencing bridge cards
• Fast DSP access to serial TDM buses
DS5026
ISSUE 2
Ordering Information
August 1998
MT90210AL
100 Pin PQFP
-40 to +85°C
Description
The MT90210 is a 100-pin device used to interface a
parallel bidirectional 8 bit bus to 24 time division
multiplexed (TDM) serial streams. The device is
configured to perform simultaneous parallel-to-serial
and serial-to-parallel conversion with the capability
of handling up to 3072 channels, 1536 on the
transmit and 1536 on the receive direction.
Depending on the operation mode selected at the
mode pins, the individual 64 Kb/s channels on the
serial links may be configured as inputs or outputs.
The data on the parallel bus is in a format suitable for
interfacing with a dual-port RAM. Depending on the
data rate selected by the MD0-MD2 input pins, serial
data is clocked in and out on the serial streams at
either 2.048, 4.096 or 8.192 Mb/s.
RDin Strobe RBC R/W1 R/W2
External Memory
S0
Access Control
•
•
•
Shift
Registers
•
•
•
•
•
Address Generator
Read
Counter
Write
Counter
Boundary
S23
Scan Test
MUX
Timing
Generation
Analog
PLL
Mode Control
P••0
P7
WBC
SCLK
HC4
C16-
C16+
F0i
PCLK
PLLVSS
LP1,LP2
PLLAGND
CKout
RST
PLLVDD
OEser MD2 MD1 MD0
Figure 1 - Functional Block Diagram
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