MT8971B Datasheet, PDF (1/20 Pages) Mitel Networks Corporation – ISO2-CMOS ST-BUS™ FAMILY Digital Subscriber Interface Circuit Digital Network Interface Circuit

ISO²-CMOS ST-BUS™ FAMILY MT8971B/72B
®
Digital Subscriber Interface Circuit
Digital Network Interface Circuit
Features
• Full duplex transmission over a single twisted
pair
• Selectable 80 or 160 kbit/s line rate
• Adaptive echo cancellation
• Up to 3km (8971B) and 4 km (8972B)
• ISDN compatible (2B+D) data format
• Transparent modem capability
• Frame synchronization and clock extraction
• MITEL ST-BUS compatible
• Low power (typically 50 mW), single 5V supply
Applications
• Digital subscriber lines
• High speed data transmission over twisted
wires
• Digital PABX line cards and telephone sets
• 80 or 160 kbit/s single chip modem
ISSUE 7
May 1995
Ordering Information
MT8971BE 22 Pin Plastic DIP
MT8972BE 22 Pin Plastic DIP
MT8972BC 22 Pin Ceramic DIP
MT8971BP 28 Pin PLCC
MT8972BP 28 Pin PLCC
-40°C to +85°C
Description
The MT8971B (DSIC) and MT8972B (DNIC) are
multi-function devices capable of providing high
speed, full duplex digital transmission up to 160
kbit/s over a twisted wire pair. They use adaptive
echo-cancelling techniques and transfer data in
(2B+D) format compatible to the ISDN basic rate.
Several modes of operation allow an easy interface
to digital telecommunication networks including use
as a high speed limited distance modem with data
rates up to 160 kbit/s. Both devices function
identically but with the DSIC having a shorter
maximum loop reach specification. The generic
"DNIC" will be used to reference both devices unless
otherwise noted.
The MT8971B/72B is fabricated in Mitel’s ISO²-
CMOS process.
DSTi/Di
CDSTi/
CDi
F0/CLD
C4/TCK
F0o/RCK
MS0
MS1
MS2
RegC
DSTo/Do
CDSTo/
CDo
Transmit
Interface
Prescrambler
Scrambler
Differentially
Encoded Biphase
Transmitter
Transmit
Filter &
Line Driver
Control
Register
Transmit
Timing
Master Clock
Phase Locked
Transmit/
Clock
Receive
Timing &
Control _{Sync Detect}
DPLL
Status
Receive
Address
Echo Canceller
Error
Signal Echo Estimate
—
+
∑
Receive
Filter
V_Bias
MUX
-1
+2
Receive
Interface
De-
Prescrambler
Descrambler
Differentially
Encoded Biphase
Receiver
V_DD V_SS V_Bias V_Ref
Figure 1 - Functional Block Diagram
L_OUT
L_OUT
DIS
Precan
L_IN
OSC2
OSC1
9-107