MT8941 Datasheet, PDF (1/18 Pages) Mitel Networks Corporation – CMOS ST-BUS™ FAMILY Advanced T1/CEPT Digital Trunk PLL

CMOS ST-BUS™ FAMILY MT8941
®
Advanced T1/CEPT Digital Trunk PLL
Features
• Provides T1 clock at 1.544 MHz locked to an 8
kHz reference clock (frame pulse)
• Provides CEPT clock at 2.048 MHz and ST-
BUS clock and timing signals locked to an
internal or external 8 kHz reference clock
• Typical inherent output jitter (unfiltered)= 0.07
UI peak-to-peak
• Typical jitter attenuation at: 10 Hz=23 dB,100
Hz=43 dB, 5 to 40 kHz ≥ 64 dB
• Jitter-free “FREE-RUN” mode
• Uncommitted two-input NAND gate
• Low power CMOS technology
Applications
• Synchronization and timing control for T1
and CEPT digital trunk transmission links
• ST- BUS clock and frame pulse source
ISSUE 5
Ordering Information
July 1993
MT8941AE
MT8941AP
24 Pin Plastic DIP
28 Pin PLCC
-40°C to +85°C
Description
The MT8941 is a dual digital phase-locked loop
providing the timing and synchronization signals for
the T1 or CEPT transmission links and the ST-BUS.
The first PLL provides the T1 clock (1.544 MHz)
synchronized to the input frame pulse at 8 kHz. The
timing signals for the CEPT transmission link and the
ST-BUS are provided by the second PLL locked to
an internal or an external 8 kHz frame pulse signal.
The MT8941 offers improved jitter performance over
the MT8940. The two devices also have some
functional differences, which are listed in the section
on “Differences between MT8941 and MT8940”.
F0i
C12i
MS0
MS1
MS2
MS3
C8Kb
C16i
Ai
Bi
DPLL #1
Mode
Selection
Logic
DPLL #2
2:1 MUX
Input
Selector
Clock
Generator
Variable
Clock
Control
Frame Pulse
Control
4.096 MHz
Clock
Control
2.048 MHz
Clock
Control
Yo
V_DD
V_SS
RST
Figure 1 - Functional Block Diagram
CVb
CV
ENCV
F0b
C4b
C4o
ENC4o
C2o
C2o
ENC2o
3-43