MT88L89 Datasheet, PDF (1/20 Pages) Mitel Networks Corporation – 3V Integrated DTMFTransceiver with Adaptive Micro Interface

®
MT88L89
3V Integrated DTMF Transceiver
Advance Information with Adaptive Micro Interface
Features
• Central office quality DTMF transmitter/
receiver
• Low voltage operation (2.7-3.6V)
• Adjustable guard time
• Automatic tone burst mode
• Call progress tone detection to -30dBm
• Adaptive micro interface enables compatibility
with existing MT8880/MT8888 designs
• DTMF transmitter/receiver power down via
register control
Applications
• Credit card systems
• Paging systems
• Repeater systems/mobile radio
• Interconnect dialers
• Personal computers
Description
The MT88L89 is a monolithic DTMF transceiver with
call progress filter. It is fabricated in CMOS
technology offering low power consumption and high
reliability.
ISSUE 1
May 1995
Ordering Information
MT88L89AE
20 Pin Plastic DIP
MT88L89AC
MT88L89AS
MT88L89AN
20 Pin Ceramic DIP
20 Pin SOIC
24 Pin SSOP
MT88L89AP
28 Pin PLCC
-40°C to +85°C
The receiver section is based upon the industry
standard MT8870 DTMF receiver while the
transmitter utilizes a switched capacitor D/A
converter for low distortion, high accuracy DTMF
signalling. Internal counters provide a burst mode
such that tone bursts can be transmitted with precise
timing. A call progress filter can be selected allowing
a microprocessor to analyze call progress tones.
The MT88L89 utilizes an adaptive micro interface,
which allows the device to be connected to a number
of popular microcontrollers with minimal external
logic. The MT88L89 provides enhanced power down
features. The transmitter and receiver may
independently be powered down via register control.
TONE
∑
D/A
Converters
IN+
IN-
GS
OSC1
OSC2
Tone Burst
Gating Cct.
+
Dial
-
Tone
Filter
Oscillator
Circuit
Bias
Circuit
Control
Logic
High Group
Filter
Low Group
Filter
Control
Logic
Row and
Column
Counters
Digital
Algorithm
and Code
Converter
Steering
Logic
Transmit Data
Register
Status
Register
Control
Register
A
Control
Register
B
Receive Data
Register
V_DD V_Ref V_SS
ESt
St/GT
Figure 1 - Functional Block Diagram
Data
Bus
Buffer
Interrupt
Logic
I/O
Control
D0
D1
D2
D3
IRQ/CP
DS/RD
CS
R/W/WR
RS0
4-125