MT8885 Datasheet, PDF (1/20 Pages) Mitel Networks Corporation – Integrated DTMFTransceiver with Power Down & Adaptive Micro Interface

MT8885
®
Integrated DTMF Transceiver
with Power Down & Adaptive
Advance Information Micro Interface
Features
• External power down pin
• Central office quality DTMF transmitter/
receiver
• Low power consumption
• High speed adaptive micro interface
• Adjustable guard time
• Automatic tone burst mode
• Call progress tone detection to -30dBm
• DTMF transmitter/receiver power down via
register control
Applications
• Credit card systems
• Paging systems
• Repeater systems/mobile radio
• Interconnect dialers
• Personal computers
Description
The MT8885 is a monolithic DTMF transceiver with
call progress filter. It is fabricated in CMOS
technology offering low power consumption and high
reliability.
ISSUE 1
May 1995
Ordering Information
MT8885AE
24 Pin Plastic DIP
MT8885AN
24 Pin SSOP
MT8885AP
28 Pin PLCC
-40°C to +85°C
The receiver section is based upon the industry
standard MT8870 DTMF receiver while the
transmitter utilizes a switched capacitor D/A
converter for low distortion, high accuracy DTMF
signalling. Internal counters provide a burst mode
such that tone bursts can be transmitted with precise
timing. A call progress filter can be selected allowing
a microprocessor to analyze call progress tones.
The MT8885 utilizes an adaptive micro interface,
which allows the device to be connected to a number
of popular microcontrollers with minimal external
logic. The MT8885 provides enhanced power down
features. The transmitter and receiver may
independently be powered down via register
control. A full chip power down pin provides simple
power and control capability.
TONE
∑
D/A
Converters
IN+
IN-
GS
OSC1
OSC2
Tone Burst
Gating Cct.
+
Dial
-
Tone
Filter
Oscillator
Circuit
Bias
Circuit
Control
Logic
High Group
Filter
Low Group
Filter
Control
Logic
Row and
Column
Counters
Digital
Algorithm
and Code
Converter
Steering
Logic
Transmit Data
Register
Status
Register
Control
Register
A
Control
Register
B
Receive Data
Register
V_DD V_Ref V_{SS PWDN}
ESt
St/GT
Figure 1 - Functional Block Diagram
Data
Bus
Buffer
Interrupt
Logic
I/O
Control
D0
D1
D2
D3
IRQ/CP
DS/RD
CS
R/W/WR
RS0
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