DAT-15575-PN Datasheet, PDF (9/12 Pages) Mini-Circuits – Digital Step Attenuator

Digital Step Attenuator
Simplified Schematic
DAT-15575-PN+
DAT-15575-PN
RF Input
RF Out
8dB
4dB
2dB
1dB
0.5dB
Parallel Control
Latch Enable
Control Logic Interface
The DAT-15575-PN parallel interface consists of 5 control bits that select the desired attenuation state, as
shown in Table 1: Truth Table
Table 1. Truth Table
Attenuation
State
C8
C4
C2
C1 C0.5
Reference
0
0
0
0
0
0.5 (dB)
0
0
0
0
1
1 (dB)
0
0
0
1
0
2 (dB)
0
0
1
0
0
4 (dB)
0
1
0
0
0
8 (dB)
1
0
0
0
0
15.5 (dB)
1
1
1
1
1
Note: Not all 32 possible combinations of C0.5 - C8 are shown
in table
The parallel interface timing requirements are defined by Figure 1 (Parallel Interface Timing Diagram) and
Table 2 (Parallel Interface AC Characteristics), and switching speed.
For latched parallel programming the Latch Enable (LE) should be held LOW while changing attenunation
state control values, then pulse LE HIGH to LOW (per Figure 1) to latch new attenuation state into device.
For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation
state control values will change device state to new attenuation. Direct mode is ideal for manual control of
the device (using hardwire, switches, or jumpers).
Figure 1: Parallel Interface Timing Diagram
LE
Parallel Data
C8:C0.5
Table 2. Parallel Interface AC Characteristics
Symbol
t_LEPW
t_PDSUP
t_PDHLD
Parameter
Min. Max.
LE minimum pulse
width
30
data set-up time before
clock rising edge of LE
10
data hold time after
clock falling edge of LE
10
Units
ns
ns
ns
t_PDSUP
t_LEPW
t_PDHLD
  




   







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