XP1006 Datasheet, PDF (5/6 Pages) Mimix Broadband – 8.5-11.0 GHz GaAs MMIC Power Amplifier

8.5-11.0 GHz GaAs MMIC
Power Amplifier
March 2006 - Rev 13-Mar-06
Bias Arrangement
Vd1a
Vgg
Vd2a
2 34
56
7
8
Vd3a
9
RF In 1
XP1006
MIMIX BROADBAND
10004966
TNO COPYRIGHT 2005
X=4940
Y=4290
10 RF Out
P1006
Bypass Capacitors - See App Note [2]
Vgg
Vd1a,2a,3a
RF In
XP1006
RF Out
18 17 16
15 14
13
12
11
Vd1b
Vd2b
Vd3b
Vd1b,2b,3b
App Note [1] Biasing - This device has been designed with an on-chip gate bias circuit. A nominal bias at Vgg=-5.0V and Vd(1,2,3)=8.0V will typically
yield a total drain current Id(TOTAL)=4.2A. It is also possible to separately bias each amplifier stage Vd1 through Vd3 at Vd(1,2,3)=8.0V with
Id1=TBDmA, Id2=TBDmA, and Id3=TBDmA. Separate biasing is recommended if the amplifier is to be used at high levels of saturation, where gate
rectification will alter the effective gate control voltage. For non-critical applications it is possible to parallel all stages and adjust the common gate
voltage for a total drain current Id(TOTAL)=4.2A. It is also recommended to use active biasing to keep the currents constant as the RF power and
temperature vary; this gives the most reproducible results. Depending on the supply voltage available and the power dissipation constraints, the
bias circuit may be a single transistor or a low power operational amplifier, with a low value resistor in series with the drain supply used to sense the
current. The gate of the pHEMT is controlled to maintain correct drain current and thus drain voltage. The typical gate voltage needed to do this is
-0.7V. Typically the gate is protected with Silicon diodes to limit the applied voltage. Also, make sure to sequence the applied voltage to ensure
negative gate bias is available before applying the positive drain supply.
App Note [2] Bias Arrangement -
For Parallel Stage Bias (Recommended for general applications) -- The same as Individual Stage Bias but all the drain or gate pad DC bypass
capacitors (~100-200 pF) can be combined. Additional DC bypass capacitance (~0.01 uF) is also recommended to all DC or combination (if gate or
drains are tied together) of DC bias pads.
For Individual Stage Bias (Recommended for saturated applications) -- Each DC pad (Vd1,2,3 and Vg1,2,3 or Vgg) needs to have DC bypass
capacitance (~100-200 pF) as close to the device as possible. Additional DC bypass capacitance (~0.01 uF) is also recommended.
MTTF Table (TBD)
These numbers were calculated based on accelerated life test information and thermal model analysis received from the fabricating foundry.
Backplate
Temperature
55 deg Celsius
75 deg Celsius
95 deg Celsius
Channel
Temperature
deg Celsius
deg Celsius
deg Celsius
Rth
MTTF Hours
FITs
C/W
E+
E+
C/W
E+
E+
C/W
E+
E+
Bias Conditions: Vd1=Vd2=Vd3=8.0V, Id(TOTAL)=4.2A
Mimix Broadband, Inc., 10795 Rockley Rd., Houston, Texas 77099
Tel: [phone] Fax: [phone] mimixbroadband.com
Page 5 of 6
Characteristic Data and Specifications are subject to change without notice. ©2006 Mimix Broadband, Inc.
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