XP1026-BD_07 Datasheet, PDF (4/5 Pages) Mimix Broadband – 27.0-32.0 GHz GaAs MMIC Power Amplifier

27.0-32.0 GHz GaAs MMIC
Power Amplifier
August 2007 - Rev 30-Aug-07
P1026-BD
App Note [1] Biasing - It is recommended to separately bias each amplifier stage Vd1 through Vd3 at Vd(1,2,3)=5.0V with Id1=100mA, Id2=250mA,
and Id3=550mA. Separate biasing is recommended if the amplifier is to be used at high levels of saturation, where gate rectification will alter the
effective gate control voltage. For non-critical applications it is possible to parallel all stages and adjust the common gate voltage for a total drain
current Id(total)=1040 mA. It is also recommended to use active biasing to keep the currents constant as the RF power and temperature vary; this
gives the most reproducible results. Depending on the supply voltage available and the power dissipation constraints, the bias circuit may be a
single transistor or a low power operational amplifier, with a low value resistor in series with the drain supply used to sense the current. The gate of
the pHEMT is controlled to maintain correct drain current and thus drain voltage. The typical gate voltage needed to do this is -0.7V. Typically the
gate is protected with Silicon diodes to limit the applied voltage. Also, make sure to sequence the applied voltage to ensure negative gate bias is
available before applying the positive drain supply.
App Note [2] Bias Arrangement -
For Parallel Stage Bias (Recommended for general applications) -- The same as Individual Stage Bias but all the drain or gate pad DC bypass
capacitors ( 100-200 pF) can be combined. Additional DC bypass capacitance ( 0.01 uF) is also recommended to all DC or combination (if gate or
drains are tied together) of DC bias pads. All DC pads have been tied together on chip and can be biased from either side.
For Individual Stage Bias (Recommended for saturated applications) -- Each DC pad (Vd1,2,3 and Vg1,2,3) needs to have DC bypass capacitance
( 100-200 pF) as close to the device as possible. Additional DC bypass capacitance ( 0.01 uF) is also recommended. All DC pads have been tied
together on chip and can be biased from either side.
MTTF Table (TBD)
These numbers were calculated based on accelerated life test information and thermal model analysis received from the fabricating foundry.
Backplate
Temperature
55 deg Celsius
75 deg Celsius
95 deg Celsius
Channel
Temperature
deg Celsius
deg Celsius
deg Celsius
Rth
MTTF Hours
FITs
C/W
E+
E+
C/W
E+
E+
C/W
E+
E+
Bias Conditions: Vd1=Vd2=Vd3=5.0V, Id1=100mA, Id2=250mA, Id3=550mA
Mimix Broadband, Inc., 10795 Rockley Rd., Houston, Texas 77099
Tel: [phone] Fax: [phone] mimixbroadband.com
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Characteristic Data and Specifications are subject to change without notice. ©2007 Mimix Broadband, Inc.
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