CFK2062-P5 Datasheet, PDF (2/5 Pages) Mimix Broadband – 2.3 to 2.5 GHz + 30 dBm Power GaAs FET

CFK2062-P5
Product Specifications
July 1997
(1 of 4)
2.3 to 2.5 GHz
+30 dBm Power GaAs FET
Features
t High Gain
t +30 dBm Power Output
t Proprietary Power FET Process
t >40% Linear Power Added Efficiency
t Surface Mount SO-8 Power Package
Applications
t ISM Band Base Stations and Terminals
t RF ID/POS Base Stations
t Wireless Local Loop
Description
The CFK2062-P5 is a high-gain FET intended for dri-
ver amplifier applications in high-power systems, and output
stage usage in medium power applications at power levels up to
+30 dBm. The device is easily matched and provides excellent
Package Diagram
GND G G GND
1234
Back Plane
is Source
8 765
GND D D GND
linearity at 1 Watt. Manufactured in Celeritek’s proprietary
power FET process, this device is assembled in an industry
standard surface mount SO-8 power package that is compatible
with high volume, automated board assembly techniques.
Specifications (TA = 25°C) The following specifications are
guaranteed at room temperature in Celeritek test fixture at 2.45 GHz.
Parameters Conditions
Vd = 8V, Id = 400 mA (Quiescent)
P-1dB
SSG
3rd Order
Products ⁽¹⁾
Efficiency @ P1dB
Vd = 5V, Id = 600 mA (Quiescent)
P-1dB
SSG
Min Typ Max Units
30.0 31.0 — dBm
12.0 13.0 — dB
— 30 — dBc
— 40 — %
— 30.5 — dBm
— 12.0 — dB
Parameters
gm
Idss
Vp
BVGD
Θ_JL (2)
Conditions
Vds = 2.0V, Vgs = 0V
Vds = 2.0V, Vgs = 0V
Vds = 3.0V, Ids = 25 mA
Igd = 2.5 mA
@150°C TCH
Min Typ Max Units
— 650 — mS
— 1.4 — A
— -1.8
Volts
15 17 — Volts
— 12 — °C/W
Absolute Maximum Ratings
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current
Continuous Dissipation
Channel Temperature
Storage Temperature
Symbol
VDS
VGS
IDS
PT
TCH
TSTG
Rating
10V ⁽³⁾
-5V
Idss
6W
175°C
-65°C to +175°C
SO-8 Power Package Physical Dimensions
Notes:
1. Sum to two tones with 1 MHz spacing = 25 dBm.
2. See thermal considerations information on page 4.
3. Maximum potential difference across the device (Vd + Vg) cannot
exceed 12V.
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