MYXN25Q512A13G12 Datasheet, PDF (7/31 Pages) –

Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
Symbol Type
Description
HOLD#
Control
Input
HOLD: Pauses any serial communications with the device without deselecting the device. DQ1 (output) is High-Z.
DQ0 (input) and the clock are Don't Care. To enable HOLD, the device must be selected with S# driven LOW. HOLD#
is used for input/output during the following operations: QUAD OUTPUT FAST READ, QUAD INPUT/OUTPUT FAST
READ, QUAD INPUT FAST PROGRAM, and QUAD INPUT EXTENDED FAST PROGRAM. In QIO-SPI, HOLD# acts as an
I/O (DQ3 functionality), and the HOLD# functionality is disabled when the device is selected. The HOLD# functionality
can be disabled using bit 4 of the NVCR or bit 4 of the VECR. On devices that include DTR mode capability, the
HOLD# functionality is disabled as soon as a DTR operation is recognized.
Write protect: W# can be used as a protection control input or in QIO-SPI operations. When in extended SPI with
single or dual commands, the WRITE PROTECT function is selectable by the voltage range applied to the signal. If
W#
Control voltage range is low (0V to V_CC), the signal acts as a write protection control input. The memory size protected against
Input PROGRAM or ERASE operations is locked as specified in the status register block protect bits 3:0. W# is used as an
input/output (DQ2 functionality) during QUAD INPUT FAST READ and QUAD INPUT/OUTPUT FAST READ operations
and in QIO-SPI.
Supply voltage: If V_PP is in the voltage range of V_PPH, the signal acts as an additional power supply, as defined in
the AC Measurement Conditions table. During QIFP, QIEFP, and QIO-SPI PROGRAM/ERASE operations, it is possible
to use the additional V_PP power supply to speed up internal operations. However, to enable this functionality, it is
V_PP
Power necessary to set bit 3 of the VECR to 0. In this case, V_PP is used as an I/O until the end of the operation. After the
last input data is shifted in, the application should apply V_PP voltage to V_PP within 200ms to speed up the internal
operations. If the V_PP voltage is not applied within 200ms, the PROGRAM/ERASE operations start at standard speed.
The default value of VECR bit 3 is 1, and the V_PP functionality for quad I/O modify operations is disabled.
V_CC
Power Device core power supply: Source voltage.
V_SS
Ground Ground: Reference for the V_CC supply voltage.
DNU
– Do not use.
NC
– No connect.
3
Memory Organization
3.1
Memory Configuration and Block Diagram
The memory is a stacked device comprised of two 256Mb chips. Each chip is internally partitioned into two
128Mb segments. Each page of memory can be individually programmed. Bits are programmed from one
through zero. The device is subsector, sector, or single 256Mb chip erasable, but not page-erasable. Bits are
erased from zero through one. The memory is configured as 67,108,864 bytes (8 bits each); 1024 sectors
(64KB each); 16,384 subsectors (4KB each); and 262,144 pages (256 bytes each); and 64 OTP bytes are
located outside the main memory array.
MYXN25Q512A13G12*
Revision 1.4 - 07/8/2015
7
Form #: CSI-D-685 Document 002