MYX4DDR2128M16PK Datasheet, PDF (3/39 Pages) Micross Components – Tin-lead ball metallurgy

2Gb DDR2 SDRAM
MYX4DDR2128M16PK*
1
Functional Block Diagram
*Advanced information. Subject to change without notice.
The DDR2 SDRAM is a high-speed CMOS, dynamic random ₂ac_Gc_bes_:s_xm₄e_,m_xo₈ry._, I_xt i₁s ₆int_Dern_Da_Rlly₂co_Sn_Dfig_Rur_Aed_Mas a
multibank DRAM.
Functional Block Diagrams
Fig^Fuⁱr^ge^u1^r:^eF⁵un^: c^Ft^uioⁿn^ca^tlⁱB^olⁿo^ack^{l B}D^li^oag^cr^kam^Di–^ag1^r2^a8^mM^–eg¹²x⁸16^{Meg x 16}
ODT
CKE
CK
CK#
CS#
RAS#
CAS#
WE#
Control
logic
Mode
registers
16
A[13:0],
BA[2:0]
16 ^Address
register
Refresh ₁₄
counter
14
3
10
14
Row-
address
MUX
Bank 7
Bank 7
Bank 6
Bank 6
Bank 5
Bank 5
Bank 4
Bank 4
Bank 3
Bank 3
Bank 2
Bank 2
Bank 1
Bank 1
Bank 0
Bank 0
row-
address
latch
16,384
Memory array
(16,384 x 256 x 64)
and
decoder
Sense amplifier
16,384
64
2
Bank
control
logic
I/O gating
DM mask logic
256
(x64)
COL0, COL1
CK, CK#
64 Read
latch
16
16
16
16
16 ^{MUX DATA}
DLL
DRVRS
DQS
4
generator _{UDQS, UDQS#}
Input ^{LDQS, LDQS#}
registers
2
2
2
WRITE ⁸ ₂
FIFO
64 ^and
Mask ₂
drivers
16
2
2
2
2
RCVRS
16
Column- 8
address
counter/
2
latch
Column
decoder
CK, CK#
CK out
CK in
64 ¹⁶
Data ¹⁶
16
COL0, COL1
16 ₁₆
16
16
4
ODT control V_DDQ
sw1 sw2 sw3
sw1 sw2 sw3
R1 R2 R3
R1 R2 R3
DQ[15:0]
sw1 sw2 sw3
R1 R2 R3
R1 R2 R3
UDQS, UDQS#
LDQS, LDQS#
sw1 sw2 sw3
R1 R2 R3
R1 R2 R3
UDM, LDM
V_SSQ
MYX4DDR2128M16PK*
Revision 1.5 - 03/27/2015
3
Form #: CSI-D-685 Document 006