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AS4DDR232M72APBG Datasheet, PDF (17/28 Pages) Micross Components – 4-bit prefetch architecture
iiPPEEMM
2.42G.4bGSb DSRDARAMM--DDDDRR22
ASA4SD4DDDRR23223M2M727A2PPBBGG
RERAEDACDOCMOMMAMNADND
TheThReERAEDAcDomcommamndanisd iussuesdetdotoiniintiaititaeteaabbuursrtstrereaaddaacccceessss
ttiiInofh=peaattiiuunohA=nbttpeo9aaAAua)nbn1ptc9ka0sratA),einecvds1ckaleteeehi0,nvctalardeeetodrnscrgwremtdtoehts.thweietnTihtesr.hemheaTesssedahietndwsadelveertrhdaaevscteirlsratunetteswlihegsundehspeg,ocrertpnooochotrhlnoveruoteihlmndtvurhreoioemdneowtdBenrBaldAoobuAlnco1neoto1oa–cinnti–taBnpigioBatnAprineouaApu0.ccntut0oshc.TitnsieaTnhAppsrAehprg0useu0ee–tevsct–idsvaihiss(alasw(wuewulerueilhgslelhleeeeecobecrdtoneersti.enss
preucsheadrg. Iefdauattotpherecehnadrgoef tihseseRleEcAteDd,btuhrestr;oiwf abuetiongparecccheasrsgeed
is nwoiltl bseelepcretecdh,atrhgeedroawt thweillernedmoafinthoepRenEAfoDr bsuurbsste; qifuaeuntto
accpersescehsa.rge is not selected, the row will remain open for
subsequent accesses.
RREERAADEDbAurODstPsOaErPeRiEnAiRtTiaAIteOTdNwIOithNa READ command. The starting
colRumEAnDanbdurbsatsnkaraeddinrietisasteeds awriethparoRviEdAedD wciothmmthaenRdE. AThDe
ctabhocuamcrsRdtsetimbtEsas.uasrAaItrebfinsDndladtegucaidastcoconfoacmoduleprumatsrtmoehsuamca.tnnohtIafdaabptainrurcaguedranetsclobdlthyiaaspaapncrrudegrcketiceesoachasihdspasbadrr.elegerrIigeftedcheash,iedussatrhetareoeegstnnpetaraharoribeebsewlcleecephdwodirat,moihorltlvgehrpbieerdldeeieeisrtsiondlaoeewabnfwntbleobaioltedfehbptdilfehnteohnegodrer,
aftethrethreowcobmepinlegtiaocncoefstsheedbisurasut.tomatically precharged at the
completion of the burst. If auto precharge is disabled, the
Durroinwg wRilEl AbeD lebfutrosptse,nthaeftevratlhide dcaotma-poleuttioenleomf ethnet fbruormst.the
staDrtiunrgincgoRluEmAnDadbdurresstss,wthilel bvealaidvadialatbal-eouRtEeAleDmlaetnetnfcroym(RtLh)e
c+aecllnlooeCds(RvccmRLtkkiELaa.esLeMrTn=)tltdithaRhncAgwetelgeeLocirvlocl.+c(MaimkbRo.lCesuRelmLu.eL,lvmaaia.aasftnoTntnleiddrdhtdrhes.Aaen,efRdLEiornvdenLMmaaersendleiiuRpsxndseteaadsCccsclfeltroyowLiotfivhrmasniealAesltelrmyLietbsdn.haueagEpeamnnraosanoddcfevgotshChCaxrf,atseiKALlmruapLesaboabmusrssnaleempaeidntiebqpdvRColucreeECofKteiogAvAnvL#riret;L)aDan.dRlmyateahlL.nagtmeaadtE=e-atMoaiCnAvbucRceLLlthey;
subsequent data-out element will be valid nominally at
DQtShe/DnQeSx#t pisodsirtiivveenobryntehgeaDtiDveR2cloScDkReAdMgeal(oi.neg.,waitththoeutnpeuxt t
datcar.oTshseinigniotiaf lCLKOWandstaCtKe #o)n. DQS and HIGH state on DQS#
is kDnQowSn/DaQsSth#eisredardivperneabmybtlhee(tRDPDRRE2).STDhRe ALMOWalostnagtewointh
DQoSuatpnudtHdIaGtaH. TsthaeteinointiaDlQLSO#WcositnacteideonntDwQithSthaendlaHstIdGaHtas-otautte
eleomnenDtQisSk#noiswnknaoswthnearseathdeporesatadmpbrleea(mtRbPlSeT()t.RPRE). The
hUapvLwoeOintbhWceoetshmnteapintleeliattiiaosottnneddDo,afQttahaSe-boauDunrQstdt,ewHalieIlslGsmguHoemnHsinttiaggithsen-Zoko.nnootDhweQnr Scao#smcmothianencdirdeseandt
postamble (tRPST).
DaUtapfroonmcaonmypRleEtiAoDn obfuarsbt murasyt,baesscuonmciantgennaoteodthweirthcodmatma faronmds
a shuabvseeqbueeennt iRnEitiAaDtedc,otmhme aDnQd wtoillpgroovHidiegha-Zco. ntinuous flow
of data. The first data element from the new burst follows the
lasDt ealteamferonmt ofaanycoRmEpAleDtedbubrusrtstm. TahyebneewcoRnEcAatDencaotmedmawnidth
shodualdtabefroismsueadsxucbysceleqsuaefntetr RthEeAfirDst cRoEmAmDacnomd mtoanpdr,owvihdeerea
x ecqounatlisnBuoLu/s2flcoywcleosf. data. The first data element from the
new burst follows the last element of a completed burst.
The new READ command should be issued x cycles after
the first READ command, where x equals BL / 2 cycles.
FIGURE 11 - READ COMMAND
FIGURE 11 – READ COMMAND
CK#
CK
CKE
CS#
RAS#
CAS#
WE#
ADDRESS
AUTO PRECHARGE
BANK ADDRESS
Col
ENABLE
A10
DISABLE
Bank
DON’T CARE
AS4DDR232M72PBG
Rev. 0.0
07/06
AS4DDR232M72APBG
Rev. 1.1 12/12
17
17
AustinSemiconductor, Inc. • (512) 339-1188 • www.austinsemiconductor.com
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