U401_TO-78 Datasheet, PDF (1/1 Pages) Micross Components – Low Noise, Low Drift, Monolithic Dual N-Channel JFET

LSU401
LOW NOISE, LOW DRIFT
MONOLITHIC DUAL
N-CHANNEL JFET
Linear Systems replaces discontinued Siliconix U401 with LSU401
The U401/ LSU401 is a Low Noise, Low Drift, Monolithic Dual N-Channel JFET
The LSU401 is a high-performance monolithic dual
JFET featuring extremely low noise, tight offset voltage
and low drift over temperature specifications, and is
targeted for use in a wide range of precision
instrumentation applications. The LSU401 features a 5-
mV offset and 10-µV/°C drift. The LSU401 is a direct
replacement for discontinued Siliconix U401.
FEATURES
LOW DRIFT
LOW NOISE
LOW PINCHOFF
ABSOLUTE MAXIMUM RATINGS
@ 25°C (unless otherwise noted)
| V _GS1‐2 / T| = 10µV/°C TYP.
e_n = 6nV/Hz @ 10Hz TYP.
V_p = 2.5V TYP.
Maximum Temperatures
The hermetically sealed TO-71 & TO-78 packages are
well suited for military applications.
Storage Temperature
Operating Junction Temperature
‐65°C to +150°C
+150°C
(See Packaging Information).
Maximum Voltage and Current for Each Transistor – Note 1
‐V_GSS
Gate Voltage to Drain or Source
50V
‐V_DSO
Drain to Source Voltage
50V
U401 / LSU401 Applications:
‐I_G(f)
Gate Forward Current
Maximum Power Dissipation
10mA
ƒ Wideband Differential Amps
ƒ High-Speed,Temp-Compensated Single-
Ended Input Amps
ƒ High-Speed Comparators
ƒ Impedance Converters and vibrations
detectors.
Device Dissipation @ Free Air – Total
300mW
MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED
SYMBOL
CHARACTERISTICS VALUE UNITS CONDITIONS
| V _GS1‐2 / T| max.
DRIFT VS.
TEMPERATURE
10 µV/°C V_DG=10V, I_D=200µA
T_A=‐55°C to +125°C
| V _GS1‐2 | max.
OFFSET VOLTAGE
5
mV V_DG=10V, I_D=200µA
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL
CHARACTERISTICS
MIN.
TYP.
MAX.
UNITS
CONDITIONS
Click ^BVGSS
BV_GGO
Y_fSS
Y_fS
Breakdown Voltage
Gate‐To‐Gate Breakdown
TRANSCONDUCTANCE
Full Conduction
Typical Operation
50
±50
2000
1000
To Buy ⁶⁰
‐‐
‐‐
‐‐
‐‐
7000
‐‐
2000
V
V
µmho
µmho
V_DS = 0
I _G= 1nA
I_D=1nA
I_D= 0
I_S= 0
V_DG= 10V
V_DG= 15V
V_GS= 0V f = 1kHz
I_D= 200µA f = 1kHz
|Y_FS1‐2 / Y _FS|
Mismatch
‐‐
0.6
3
%
DRAIN CURRENT
I_DSS
Full Conduction
0.5
‐‐
10
mA
V_DG= 10V
V_GS= 0V
|I_DSS1‐2 / I_DSS| Mismatch at Full Conduction
‐‐
1
5
%
GATE VOLTAGE
V_GS(off) or V_p
Pinchoff voltage
‐0.5
‐‐
‐2.5
V
V_DS= 15V
I_D= 1nA
V_GS(on)
Operating Range
‐‐
‐‐
‐2.3
V
V_DS=15V
I_D=200µA
GATE CURRENT
‐I_Gmax.
Operating
‐‐
‐4
‐15
pA
V_DG= 15V I_D= 200µA
‐I_Gmax.
‐I_GSSmax.
High Temperature
At Full Conduction
‐‐
‐‐
‐10
‐‐
‐‐
100
nA
T_A= +125°C
pA
V_DS =0
‐I_GSSmax.
High Temperature
5
5
5
pA
V_DG= 15V T_A= +125°C
OUTPUT CONDUCTANCE
Y_OSS
Full Conduction
‐‐
‐‐
20
µmho
V_DG= 10V
V_GS= 0V
Y_OS
Operating
‐‐
0.2
2
µmho
V_DG= 15V
I_D= 500µA
COMMON MODE REJECTION
CMR
‐20 log | V _GS1‐2/ V _DS|
95
‐‐
‐‐
dB
V_DS = 10 to 20V I_D=30µA
NOISE
V_DS= 15V V_GS= 0V R_G= 10M
NF
Figure
‐‐
‐‐
0.5
dB
f= 100Hz NBW= 6Hz
e_n
Voltage
‐‐
20
‐‐
nV/√Hz
V_DS=15V I_D=200µA f=10Hz NBW=1Hz
CAPACITANCE
C_ISS
Input
‐‐
‐‐
8
pF
V_DS= 15V I_D= 200µA f= 1MHz
C_RSS
Reverse Transfer
‐‐
‐‐
1.5
pF
Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired
TO-71 / TO-78 (Top View)
Micross Components Europe
Available Packages:
U401 / LSU401 in TO-71 & TO-78
U401 / LSU401 available as bare die
Please contact Micross for full package and die dimensions
Tel: [phone]
Email: [e-mail]
Web: http://www.micross.com/distribution
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.