SD210DE Datasheet, PDF (1/1 Pages) Linear Integrated Systems – HIGH SPEED DMOS FET ANALOG SWITCHES AND SWITCH ARRAYS

SD210 / SD214
SD210DE / SD214DE series N-Channel Enhancement Mode DMOS Lateral Switches
Description:
The SD210DE & SD214DE are enhancement‐mode MOSFETs designed
for high speed low‐glitch switching in audio, video and high‐
frequency applications. The SD214DE is normally used for ±10V
analog switching. These MOSFETs utilize lateral construction to
achieve low capacitance and ultra‐fast switching speeds. These
MOSFETs do not have a gate protection Zener diode which results in
lower gate leakage and ± voltage capability from gate to substrate. A
poly‐silicon gate is featured for manufacturing reliability.
See SD5000 and SD54000 series for quad configurations.
For zener protected versions see SD211DE / SST211 series
Features:
ƒ Ultra‐High Speed Switching—tON: 1ns
ƒ Ultra‐Low Reverse Capacitance: 0.2pF
ƒ Low Guaranteed R_DS @5V
ƒ Low Turn‐On Threshold Voltage (1.5V max)
ƒ N‐Channel Enhancement Mode
Benefits:
ƒ High‐Speed System Performance
ƒ Low Insertion Loss at High Frequencies
ƒ Low Transfer Signal Loss
ƒ Single Supply Operation & Simple Driver Requirement
Availability:
SD210DE – TO‐72 hermetic package, ‐55°C to +125°C
SD214DE – TO‐72 hermetic package, ‐55°C to +125°C
SD210DE / SD214DE ‐ Bare die form
Contact Micross for full package dimensions
Pinout:
SD210 / SD214 Applications:
ƒ Fast Analog Switching
ƒ Fast Sample & Holds
ƒ Pixel‐Rate Switching
ƒ DAC Deglitchers
ƒ High‐Speed Driver
MAXIMUM RATINGS
LIMIT
MAXIMUM RATINGS
LIMIT
UNIT
SD210DE
SD214DE
(Continued)
Gate‐Drain, Gate‐Source Voltage
±40V
±40V
Drain Current
50
mA
Gate‐Substrate Voltage
±30V
±30V
Lead Temperature (1/16” from ease, 10s)
300
°C
Drain‐Source Voltage
30V
20V
Storage Temperature
‐65 to 150 °C
Source‐Drain Voltage
10V
20V
Operating Junction Temperature
‐55 to 125 °C
Drain ‐Substrate Voltage
30V
25V
Power Dissipation
Click To Buy ^{Source‐Substrate Voltage}
15V
ELECTRICAL SPECIFICATION
T_A = 25°C unless otherwise noted
SYMBOL
25V
Derate 3mW/C° above 25°C
300
TEST CONDITIONS
LIMITS
TYP
SD210DE
SD214DE
MIN MAX MIN MAX
mW
UNIT
DRAIN‐SOURCE BREAKDOWN
VOLTAGE
V_(BR)DS
V_GS = V_BS = 0V, I_D = 10µA
V_GS = V_BS = ‐5V, I_D = 10nA
35 30
‐
‐
‐
30 10
‐
20
‐
SOURCE‐DRAIN BREAKDOWN
VOLTAGE
DRAIN‐SUBSTRATE BREAKDOWN
VOLTAGE
V_(BR)SD
V_(BR)DBO
V_GD = V_BD = ‐5V, I_S = 10nA
V_GB = 0V, I_D = 10nA
Source Open
22 10
‐
20
‐
V
35 15
‐
25
‐
SOURCE‐SUBSTRATE BREAKDOWN
VOLTAGE
V_(BR)SBO
V_GB = 0V, I_S = 10µA
Drain Open
35 15
‐
25
‐
DRAIN‐SOURCE LEAKAGE
SOURCE‐DRAIN LEAKAGE
GATE LEAKAGE
I_DS(off)
I_SD(off)
I_GBS
V_GS = V_BS = ‐5V
V_DS = 10V
0.4
‐
10
‐
‐
V_DS = 20V
0.9
‐
‐
‐
10
V_GD = V_BD = ‐5V
V_SD = 10V
0.5
‐
10
‐
‐
nA
V_SD = 20V
0.8
‐
‐
‐
10
V_DB = V_SB = 0V _, V_GB = ±4 0V
0.001 ‐
0.1
‐
0.1
THRESHOLD VOLTAGE
V_GS(th)
V_DS = V_{GS ,} I_D = 1µA, V_SB = 0V
0.8 0.5 1.5 0.1 1.5
V_GS = 5V
58
‐
70
‐
70
DRAIN‐SOURCE‐ON RESISTANCE
R_DS(on)
V_GS = 10V
38
‐
45
‐
45
V_SB = 0V_, I_D = 1mA
V_GS = 15V
30
‐
‐
‐
‐
Ω
V_GS = 20V
26
‐
‐
‐
‐
V_GS = 25V
24
‐
‐
‐
‐
FORWARD TRANSCONDUCTANCE
g_fs
V_DS = 10V _, V_SB = 0V
11 10
‐
10
‐
mS
g_os
I_D = 20mA, f = 1kHz
0.9
‐
‐
‐
‐
GATE NODE CAPACITANCE
C_(GS+GD+GB)
2.5
‐
3.5
‐
3.5
DRAIN NODE CAPACITANCE
C_(GD+GB)
V_DS = 10V _, f = 1MHz
1.1
‐
1.5
‐
1.5
SOURCE NODE CAPACITANCE
C_(GS+SB)
V_GS = V_BS = ‐15V
3.7
‐
5.5
‐
5.5
pF
REVERSE TRANSFER CAPACITANCE
C_rss
0.2
‐
0.5
‐
0.5
TURN‐ON TIME
t_D(on)
0.5
‐
1
‐
1
t_r
V_SB = 0V_, V_IN 0 to 5V,
0.6
‐
1
‐
1
ns
TURN‐OFF TIME
t_D(off)
R_G = 25Ω, V_DD = 5V R_L = 680Ω
2
‐
‐
‐
‐
This is trial version ^tf
6
‐
‐
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