LS843_SOIC Datasheet, PDF (1/1 Pages) Micross Components – Linear Systems Ultra Low Leakage Low Drift Monolithic Dual JFET

LS843
MONOLITHIC DUAL
N-CHANNEL JFET
Linear Systems Ultra Low Leakage Low Drift Monolithic Dual JFET
The LS843 is a high-performance monolithic dual
JFET featuring extremely low noise, tight offset voltage
and low drift over temperature specifications, and is
targeted for use in a wide range of precision
instrumentation applications. The LS843 features a 1-
mV offset and 5-µV/°C drift.
FEATURES
LOW DRIFT
| V _GS1‐2 / T| ≤5µV/°C
LOW LEAKAGE
LOW NOISE
I_G = 15pA TYP.
e_n = 3nV/√Hz TYP.
LOW OFFSET VOLTAGE
| V _GS1‐2| ≤1mV
ABSOLUTE MAXIMUM RATINGS @ 25°C (unless otherwise noted)
The 8 Pin P-DIP and 8 Pin SOIC provide ease of
manufacturing, and the symmetrical pinout prevents
improper orientation.
(See Packaging Information).
LS843 Applications:
ƒ Wideband Differential Amps
ƒ High-Speed,Temp-Compensated Single-
Ended Input Amps
ƒ High-Speed Comparators
ƒ Impedance Converters and vibrations
detectors.
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL
CHARACTERISTICS
MIN.
BV_GSS
Breakdown Voltage
60
BV_GGO
Gate‐To‐Gate Breakdown
60
TRANSCONDUCTANCE
Click ^YfSS
Y_fS
|Y_FS1‐2 / Y _FS|
I_DSS
Full Conduction
Typical Operation
Mismatch
DRAIN CURRENT
Full Conduction
1500
1000
‐‐
1.5
|I_DSS1‐2 / I_DSS| Mismatch at Full Conduction
‐‐
GATE VOLTAGE
V_GS(off) or V_p
Pinchoff voltage
1
V_GS(on)
Operating Range
0.5
GATE CURRENT
‐I_Gmax.
Operating
‐‐
‐I_Gmax.
High Temperature
‐‐
‐I_Gmax.
Reduced V_DG
‐‐
‐I_GSSmax.
At Full Conduction
‐‐
OUTPUT CONDUCTANCE
Y_OSS
Full Conduction
‐‐
Y_OS
Operating
‐‐
|Y_OS1‐2|
Differential
‐‐
COMMON MODE REJECTION
CMR
‐20 log | V _GS1‐2/ V _DS|
90
‐20 log | V _GS1‐2/ V _DS|
‐‐
NOISE
NF
Figure
‐‐
e_n
Voltage
‐‐
‐‐
CAPACITANCE
C_ISS
Input
‐‐
C_RSS
Reverse Transfer
‐‐
C_DD
Drain‐to‐Drain
‐‐
Maximum Temperatures
Storage Temperature
‐65°C to +150°C
Operating Junction Temperature
+150°C
Maximum Voltage and Current for Each Transistor – Note 1
‐V_GSS
Gate Voltage to Drain or Source
‐V_DSO
Drain to Source Voltage
‐I_G(f)
Gate Forward Current
Maximum Power Dissipation
60V
60V
50mA
Device Dissipation @ Free Air – Total
400mW @ +125°C
MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED
SYMBOL
CHARACTERISTICS VALUE UNITS CONDITIONS
| V _GS1‐2 / T| max.
| V _GS1‐2 | max.
DRIFT VS.
TEMPERATURE
OFFSET VOLTAGE
5 µV/°C V_DG=10V, I_D=500µA
T_A=‐55°C to +125°C
1
mV V_DG=10V, I_D=500µA
TYP.
MAX.
‐‐
‐‐
‐‐
‐‐
UNITS
V
V
CONDITIONS
V_DS = 0
I _G= 1nA
I_D=1nA
I_D= 0
I_S= 0
To Buy ^‐‐
‐‐
1500
‐‐
0.6
3
5
15
µmho
µmho
%
mA
V_DG= 15V
V_DG= 15V
V_GS= 0V f = 1kHz
I_D= 500µA
V_DG= 15V
V_GS= 0V
1
5
%
‐‐
3.5
‐‐
3.5
15
50
‐‐
50
5
30
‐‐
100
‐‐
20
0.2
2
0.02
0.2
V
V
pA
nA
pA
pA
µmho
µmho
µmho
V_DS= 15V
V_DS=15V
I_D= 1nA
I_D=500µA
V_DG= 15V I_D= 500µA
T_A= +125°C
V_DG = 3V I_D= 500µA
V_DG= 15V , V_DS =0
V_DG= 15V
V_DG= 15V
V_GS= 0V
I_D= 500µA
110
‐‐
85
‐‐
‐‐
0.5
‐‐
7
‐‐
11
‐‐
8
‐‐
3
0.5
‐‐
dB
dB
nV/√Hz
pF
∆V_DS = 10 to 20V I_D=500µA
∆V_DS = 5 to 10V I_D=500µA
V_DS= 15V V_GS= 0V R_G= 10MΩ
f= 100Hz NBW= 6Hz
V_DS=15V I_D=500µA f=1KHz NBW=1Hz
V_DS=15V I_D=500µA f=10Hz NBW=1Hz
V_DS= 15V, I_D=500µA
V_DG= 15V, I_D=500µA
Note 1 – These ratings are limiting values above which the serviceability of any semiconductor may be impaired
PDIP & SOIC (Top View)
Available Packages:
LS843 / LS843 in PDIP & SOIC
LS843 / LS843 available as bare die
Please contact Micross for full package and die dimensions
Tel: [phone]
Email: [e-mail]
Web: http://www.micross.com/distribution
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