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LS842_TO-78 Datasheet, PDF (1/1 Pages) Micross Components – MONOLITHIC DUAL N-CHANNEL JFET | |||
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LS842
MONOLITHIC DUAL
N-CHANNEL JFET
Linear Systems Ultra Low Leakage Low Drift Monolithic Dual JFET
The LS842 is a high-performance monolithic dual
JFET featuring extremely low noise, tight offset voltage
and low drift over temperature specifications, and is
targeted for use in a wide range of precision
instrumentation applications. The LS842 features a 25-
mV offset and 40-µV/°C drift.
FEATURES
LOW DRIFT
| V GS1â2 / T| â¤40µV/°C
LOW LEAKAGE
LOW NOISE
IG = 10pA TYP.
en = 8nV/âHz TYP.
LOW OFFSET VOLTAGE
| V GS1â2| â¤25mV
ABSOLUTE MAXIMUM RATINGS @ 25°C (unless otherwise noted)
The hermetically sealed TO-71 & TO-78 packages are
well suited for military and harsh environment
applications.
(See Packaging Information).
LS842 Applications:
 Wideband Differential Amps
 High-Speed,Temp-Compensated Single-
Ended Input Amps
 High-Speed Comparators
 Impedance Converters and vibrations
detectors.
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL
CHARACTERISTICS
MIN.
BVGSS
Breakdown Voltage
60
BVGGO
GateâToâGate Breakdown
60
TRANSCONDUCTANCE
Click YfSS
YfS
|YFS1â2 / Y FS|
IDSS
Full Conduction
Typical Operation
Mismatch
DRAIN CURRENT
Full Conduction
1000
500
ââ
0.5
|IDSS1â2 / IDSS| Mismatch at Full Conduction
ââ
GATE VOLTAGE
VGS(off) or Vp
Pinchoff voltage
1
VGS(on)
Operating Range
0.5
GATE CURRENT
âIGmax.
Operating
ââ
âIGmax.
High Temperature
ââ
âIGmax.
Reduced VDG
ââ
âIGSSmax.
At Full Conduction
ââ
OUTPUT CONDUCTANCE
YOSS
Full Conduction
ââ
YOS
Operating
ââ
|YOS1â2|
Differential
ââ
COMMON MODE REJECTION
CMR
â20 log | V GS1â2/ V DS|
ââ
â20 log | V GS1â2/ V DS|
ââ
NOISE
NF
Figure
ââ
en
Voltage
ââ
ââ
CAPACITANCE
CISS
Input
ââ
CRSS
Reverse Transfer
ââ
CDD
DrainâtoâDrain
ââ
Maximum Temperatures
Storage Temperature
â65°C to +150°C
Operating Junction Temperature
+150°C
Maximum Voltage and Current for Each Transistor â Note 1
âVGSS
Gate Voltage to Drain or Source
âVDSO
Drain to Source Voltage
âIG(f)
Gate Forward Current
Maximum Power Dissipation
60V
60V
50mA
Device Dissipation @ Free Air â Total
400mW @ +125°C
MATCHING CHARACTERISTICS @ 25°C UNLESS OTHERWISE NOTED
SYMBOL
CHARACTERISTICS VALUE UNITS CONDITIONS
| V GS1â2 / T| max.
| V GS1â2 | max.
DRIFT VS.
TEMPERATURE
OFFSET VOLTAGE
40 µV/°C VDG=20V, ID=200µA
TA=â55°C to +125°C
25
mV VDG=20V, ID=200µA
TYP.
MAX.
60
ââ
ââ
ââ
UNITS
V
V
CONDITIONS
VDS = 0
I G= 1nA
ID=1nA
ID= 0
IS= 0
To Buy ââ
4000
ââ
1000
0.6
3
2
5
µmho
µmho
%
mA
VDG= 20V
VDG= 20V
VGS= 0V f = 1kHz
ID= 200µA
VDG= 20V
VGS= 0V
1
5
%
2
4.5
ââ
4
10
50
ââ
50
5
ââ
ââ
100
ââ
10
0.1
1
0.01
0.1
V
V
pA
nA
pA
pA
µmho
µmho
µmho
VDS= 20V
VDS=20V
ID= 1nA
ID=200µA
VDG= 20V ID= 200µA
TA= +125°C
VDG = 10V ID= 200µA
VDG= 20V , VDS =0
VDG= 20V
VDG= 20V
VGS= 0V
ID= 200µA
100
ââ
75
ââ
ââ
0.5
ââ
10
ââ
15
10
4
1.2
5
0.1
ââ
dB
dB
nV/âHz
pF
âVDS = 10 to 20V ID=200µA
âVDS = 5 to 10V ID=200µA
VDS= 20V VGS= 0V RG= 10MΩ
f= 100Hz NBW= 6Hz
VDS=20V ID=200µA f=1KHz NBW=1Hz
VDS=20V ID=200µA f=10Hz NBW=1Hz
VDS= 20V, ID=200µA
Note 1 â These ratings are limiting values above which the serviceability of any semiconductor may be impaired
TO-71 & TO-78 (Top View)
Available Packages:
LS842 / LS842 in TO-78 & TO-71
LS842 / LS842 available as bare die
Please contact Micross for full package and die dimensions
Tel: +44 1603 788967
Email: chipcomponents@micross.com
Web: http://www.micross.com/distribution
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.
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